We present a framework for combining Voltage Scaling and Gate sizing techniques for power optimizations. Our results show that the combination of the two techniques perform better than the techniques applied in isolation. We introduce a new heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate esti...

In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18μm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circui...

An architecture for a time interpolation circuit with an rms error of 25 ps has been developed in a 0.7m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage depend...

The purpose of this project is to lower the power consumption by reducing the operating voltage of a 32-bit adder, implemented with TSMC035 technology. The delay and power dissipation of the circuit at different voltages were studied and based on the power delay product an optimal voltage of operation was chosen. A level converter circuit was designed, in order to make the circuit compatible wi...

In this paper, the circuit performances such as circuit delay, RF characteristics and SRAM static noise margin are presented. These analyses are performed by threedimensional device simulation using Mixed-mode option. The benefit of circuit delay in scaling will be maintained by introducing new structure (SOI, multi-gate), material (silicide, metal gate) and strain effect. However, concerning w...

This paper gives an approach for improvement in the reduction in delay variation in a domino logic circuits and it also gives improved noise immunity to the circuit. The improvement in delay observed here is better in the proposed circuit and the noise immunity is also enhanced by a good margin. The simulation process here is done by using Cadence Virtuoso 65nm process technology at 27 o C oper...

We present an algorithm that computes a Boolean circuit for an AND-OR path (i.e., a formula of type t0∧(t1∨(t2∧(. . . tm−1) . . . ) or t0∨(t1∧(t2∨(. . . tm−1) . . . )) with given arrival times for the input signals. Our objective function is delay, a generalization of depth. The maximum delay of the circuit we compute is log2 W+log2 log2 m+log2 log2 log2 m+5, where dlog2 W e is a lower bound on...

The identiication of sensitizable paths and the determination of path delays play key roles in many delay fault testing schemes. In this paper we examine a range of gate delay models with respect to their impact on identifying both sensitizable paths and maximum circuit delays in com-binational logic circuits. We provide recommendations on the \minimum acceptable" model for identifying critical...

This paper describes a transistor sizing methodology for both analog and digital CMOS circuits. Various techniques are used for power optimization in CMOS VLSI circuits. Transistor sizing is one of the important techniques for the determination of circuit performance. The aim of the power optimization is to minimize the power and power-delay product or the energy consumption of the circuit. Thu...

In this paper, we propose an iterative area/delay tradeoff algorithm to solve the circuit clustering problem under the capacity constraint. It first finds an initial delay-considered area-optimized clustering solution by a delay-oriented depthfirst-search procedure. Then, an iterative procedure consisting of several reclustering techniques is applied to gradually trade the area for the performa...