The decreasing dimensions of IC devices is rendering the heat diffusion equation highly inaccurate for simulations of electrostatic discharge (ESD) phenomena. As dimensions of the heated region in the device are reduced far below 200 nm, neglecting the ballistic, sub-continuum nature of phonon conduction in the silicon lattice can strongly underpredict the temperature rise. This work integrates...

This work introduces a numerical method to iteratively extract parameters of rectangular parallelepiped (RPP) sensitive volume (SV) from experimental proton direct ionization (PDI) SEU data. The combines two separate models. first model estimates the average linear energy transfer (LET) values for energetic ions, including protons and also heavy in elemental solid targets. second describes stat...

We propose a technique, using interferometry of Bose-Einstein condensed alkali atoms, for the detection of sub-micron-range forces. It may extend present searches at 1 micron by 6 to 9 orders of magnitude, deep into the theoretically interesting regime of 1000 times gravity. We give several examples of both four-dimensional particles (moduli), as well as higher-dimensional particles – vectors a...

Introduction: Charge-coupled devices (CCDs) have conventionally used overlapping (0.5–2.5 mm) polysilicon gates to achieve charge transfer between gates with a very high charge transfer efficiency (CTE) [1]. Since conventional CMOS processes do not allow poly-overlaps, it was not possible to achieve a ‘true’ CCD structure in this process until now, though efforts were made in this direction [2]...

Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characteriz...

The effects of charged particles striking VLSI circuits and producing single event transients (SETs) are becoming an issue for designers who exploit deep sub-micron technologies; efficient and accurate techniques for assessing their impact on VLSI designs are thus needed. This paper presents a new approach for generating the list of faults to be addressed during fault injection experiments tack...

In this paper, we present the temperature based simulation and analysis of gate leakage current for the proposed low-stress IP3 SRAM bit cell. In CMOS technologies, cache memory occupies a large die area and this may experience different temperatures. Under temperature variations, performance of the system may degrade. Therefore, in the IP3 SRAM cell, gate leakage has been analyzed under temper...

For System-on-Chip (SoC) using deep sub-micron technologies, semiglobal and global interconnects are susceptible to crosstalk defects that may lead to mal-function and timing failures. Removal of crosstalk defects is becoming important to ensure error-free operation of an SoC. To efficiently evaluate crosstalk-defect coverage, it is necessary to understand the factors affecting this noise. In t...

The demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks has been introducing a new chip design paradigm so called on chip network. This paradigm promisingly offers a packet switched network among IPs to reduce the main problems in the very deep sub micron technologies that arise from non-scalable global wire delay, failure to achieve global synchronizatio...

The availability of reusable IP-cores, increasing timeto-market and design productivity gap, and enabling deep sub-micron technologies have led to core-based system-onchip (SoC) design as a new paradigm in electronic system design. Validation of these complex hardware/software systems is the most time consuming task in the design flow. In this paper, we focus on developing an efficient interfac...