Edge computing is becoming increasingly popular in artificial intelligence (AI) application development due to the benefits of local execution. One widely used approach overcome hardware limitations edge heterogeneous computing, which combines a general-purpose processor with domain-specific AI processor. However, this can be inefficient communication overhead resulting from complex protocol. T...

It is not always feasible to implement an application specific custom hardware due to cost and time considerations. No instruction set compiler (NISC) architecture is one of the promising directions to design a custom datapath for each application using its execution characteristics. A major challenge with NISC control words is that they tend to be at least 4–5 times larger than regular instruc...

Driving FPGA systems from ANSI C is possible using lcc (a retargetable ANSI C compiler) targeted at an FPGA system and dasm (a retargetable, exible assembler) tools. The compiler supports custom hardware capabilities of FPGA systems, as well as all constructs of C. The assembler reads instruction de nitions at assemble time, allowing the user to add new custom hardware functions which dasm can ...

In this paper, we present a technique for custom instruction (CI) extension considering process variations. The technique bridges the gap between the high level custom instruction extension and chip fabrication in nanotechnologies. In particular, instead of using the conventional static timing analysis (STA), it utilizes statistical static timing analysis (SSTA). Therefore, the approach becomes...

This artifact is based on Weverca, a static analyzer framework for PHP applications. The aim of Weverca is to provide developers with a framework that would allow for an easy implementation of custom static analyses of PHP, while not coping with the dynamic language issues. The framework processes the input source code in two phases. In the first phase, the program-point graph is constructed, w...

This work quantifies the performance benefit of vectorized versions of the ITU-T G.729A and G.723.1 speech coding standards. Architecture-level experimentation with the addition of custom vector instructions indicates a reduction in the dynamic instruction count of the workloads of the order of 51% and 65% respectively at a vector register length of sixteen 16-bit elements. The identified vecto...

The Advanced Encryption Standard (AES) specifies an algorithm for a symmetric-key cryptosystem that has already found wide adoption in security applications. A substantial part of the AES algorithm are the MixColumns and InvMixColumns operations, which involve multiplications in the binary extension field GF(2). Recently proposed instruction set extensions for elliptic curve cryptography (ECC) ...

Extensible processors allow customization for an application by extending the core instruction set architecture. Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit. Custom instructions (CIs) usually are extracted from critical portions of applications. This paper presents approaches fo...

A wavelet-based image-encoding is described which, when used in conjunction with the Diierence Engine (a custom-designed VLSI display processor) allows us to reconstruct an image in real-time without the need to set each pixel explicitly. The image is compressed using a quadratic spline-wavelet transform; when reconstructing, an image-adaptive instruction generator attempts to produce the minim...