A low-voltage and low-power current mode analog multiplier/divider design is presented in this paper. The based on operational transconductance amplifier (OTA) utilizing dynamic threshold MOS (DTMOS) structure consists of only three OTAs. circuit has the ability consuming low power requiring voltage supplies. 0.13µm IBM CMOS technology parameters are used to simulate suggested simulation result...

We propose the design of an analog Interval Type-2 (IT2) fuzzy logic controller chip that is based on the realization approach of averaging of two Type-1 Fuzzy Logic Systems (T1 FLSs). The fuzzifier is realized using transconductance mode membership function generator circuits. The membership functions are made tunable by setting some reference voltages on the IC pins. The inference is realized...

In this note we examine the change of the PMT pulse gain as a function of DC background current using an active divider and compare its behavior to the one obtained using a passive network. We show that the present version of the active divider results in: 1) constant gain over a large background current (rendering possible to operate the FD under the presence of some backscattered moon light, ...

In this paper design and simulation of a 4.3 – 5.4 GHz LC digitally controlled oscillator (LC DCO) in IBM 7RF 0.18μm CMOS technology are presented. Wide gigahertz tuning range is achieved by using two LC DCOs, sharing same structure. DCO is made of one NMOS negative impedance transistor pair and LC tank, which consists of high quality inductor and two switched capacitor arrays for coarse and fi...

The behavior of two frequency divider circuits using negative differential resistance (NDR) circuit is studied. This NDR circuit is made of three resistors (R) and two bipolar-junction-transistor (BJT) devices. It can show the NDR characteristic in its current-voltage curve by suitably designing the resistances. We discuss a dynamic frequency divider, which is made of a R-BJT-NDR circuit, an in...

This paper presents a new simple configuration to realize the voltage-controlled floating resistor, which is suitable for integrated circuit implementation. The proposed resistor is composed of three main components: MOS transistor operating in the non-saturation region, DDCC, and MOS voltage divider. The MOS transistor operating in the non-saturation region is used to configure a floating line...

This paper presents a low-power fractional-N synthesizer for BLE with gate-switching charge pump (CP) and high-speed prescaler. To reduce the current mismatch under low supply voltage, master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is employed to CP; Current self-matching technique guarantees charging equal discharging current. The embedded logic gates power s...

A novel coupled-line structure is proposed to design dual-band and high-power Gysel power dividers with inherent impedance-transforming functions. Based on traditional even- and odd-mode technique, the analytical design methods in closed-form formula are obtained and the accurate electrical parameters analysis is presented. Due to the usage of coupled-line sections, more design-parameter freedo...

A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a resul...