1. Queueuing Device – typically residing on the line card, this device is responsible for hosting the virtual output queues (VOQ) and managing control processes such as flow control. 2. Crosspoint Switch – a matrix cross-connecting element through which packets traverse to reach their designated output ports. 3. Scheduler – acting as the “brain” of the system, it is this device that determines ...

The apparatus of the Generalized Nets (GN) is applied to describe LPF-algorithm for modeling a conflict-free schedule packet crossbar switch. Throughput calculation results switch node with LPF- algorithm computer simulation family load traffic patterns are presented. Studies show that execution time depends on degree dimension O(n exp(4,7)). necessary computations have been implemented AVITOHO...

Cache coherent non-uniform memory access (CC-NUMA) multiprocessors provide a scal-able design for shared memory but they continue to suuer from large remote memory access latencies due to comparatively slow memory technology and data transfer latencies in the in-terconnection network. In this paper, we propose a novel hardware caching technique, called switch cache, to improve the remote memory...

ÐCache coherent nonuniform memory access (CC-NUMA) multiprocessors provide a scalable design for shared memory. But, they continue to suffer from large remote memory access latencies due to comparatively slow memory technology and large data transfer latencies in the interconnection network. In this paper, we propose a novel hardware caching technique, called switch cache, to improve the remote...

Buffered crossbars have been considered as an alternative for non-buffered crossbars to improve switching throughput. The drawback of a buffered crossbar is the memory amount that is proportional to the square of the number of ports (O N ). This is not the main limitation when the buffer size is kept to a minimum size such that implementation is feasible. For a small buffer size, the number of ...

We show an isomorphism between packet scheduling in crossbar switches and circuit switching in three-stage Clos networks, using the concept of rate quantization. We use the analogy for a crossbar switch of size n×n to construct a simple packet scheduler of complexity O(n logn) based on maximal matching. We show that, with this simple scheduler, a speedup of O(logn/ log logn) is necessary to sup...

MEMS optical switch technology is one of the key technologies in Wavelength Division Multiplexing (WDM) optical networks. Although the 2-D MEMS optical switch technology is mature, the commonly used crossbar architecture is not amenable to building large switches. In this paper, we propose a design of 2 × 2 switching modules, and use it to build large 2-D MEMS optical switches with architecture...

Large input-output buffering with a moderate speedup has been widely considered as the most feasible solution for large-capacity switches. We propose a new terabit per second packet switch and call it the Saturn switch. It uses a simple dual round-robin arbitration scheme to schedule packets, and achieves high throughput and low statistical delay bound. It employs a bit-sliced crossbar fabric t...

The combined input and crossbar queued (CICQ) switch is an input buffered switch suitable for very high-speed networks. The implementation feasibility of the CICQ switch architecture for 24 ports and 10-Gbps link speed is shown in this paper with an FPGA-based design (estimated cost of $30,000 in mid-2002). The bottleneck of a CICQ switch with RR scheduling is the RR poller. We develop a priori...

Cache coherentnon-uniform memory access (CC-NUMA) multiprocessors continue to suffer from remote memory access latencies due to comparatively slow memory technology and data transfer latencies in the interconnection network. In this paper, we propose a novel hardware caching technique, called switch cache. The main idea is to implement small fast caches in crossbar switches of the interconnect ...