Coordinate rotation digital computer (CORDIC) is an efficient algorithm for computations of trigonometric functions. Scaling-free-CORDIC is one of the famous CORDIC implementations with advantages of speed and area. In this paper, a novel direct digital frequency synthesizer (DDFS) based on scaling-free CORDIC is presented. The proposed multiplier-less architecture with small ROM and pipeline d...

We present a radix-10 variant of the BKM algorithm. It is a shift-and-add, CORDIC-like algorithm that allows fast computation of complex exponentials and logarithms. This radix-10 version is suitable for implementation in a pocket computer. Key-words: Elementary functions, CORDIC algorithms, Computer Arithmetic, radix10 arithmetic

In [1], Duprat and Muller introduced the ingenious “Branching CORDIC” algorithm. It enables a fast implementation of CORDIC algorithm using signed digits and requires a constant normalization factor. This correspondence corrects some errors in the original paper. All the page numbers quoted are from [1].

New, efficient, 8-D rotation CORDIClike algorithms for matrix computations are presented. These algorithms are a natural extension to 8 dimensions of Quaternion CORDIC algorithms, offered by J.M. Delosme and S.F. Hsiao. This leads to significantly reduced computations in contrast to 8-D Householder CORDIC algorithms given by the same authors. Such algorithms may be utilized for designing VLSI a...

The compensation of scale factor imposes significant computation overhead on the CORDIC algorithm. In this paper we present two algorithms and the corresponding architectures (one for both rotation and vectoring modes and the other only for rotation mode) to perform the scaling factor compensation in parallel with the classical CORDIC iterations. With these methods, the scale factor compensatio...

We present a fixed point architecture (source VHDL code is provided) for powering computation. The fully customized architecture, based on the expanded hyperbolic CORDIC algorithm, allows for design space exploration to establish tradeoffs among design parameters (numerical format, number of iterations), execution time, resource usage and accuracy. We also generate Pareto-optimal realizations i...

| Cordic based IIR digital lters possess desirable properties for VLSI implementation such as local connection, regularity, and good-nite word-length behavior, but can't be pipelined to ner levels (such as bit or multi-bit levels) due to the presence of feedback loops. In this paper, a pipelining method for the cordic based IIR digital lters is proposed using the constrained lter design methods...

One of the main problems of the CORDIC algorithm is the limited convergence domain, in which the functions can be calculated. Two different approaches can be employed to overcome this constraint: first, an argument reduction method and, second, an expansion of the CORDIC convergence domain. While the first approach requires significant processing overhead due to the need for divisions, the seco...