We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric pr...

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In this paper a new high gain bandwidth (GBW) and low power folded cascade OPAMP is presented. It has been implemented and layouted by CADENCE software in 0.18μm. Its DC gain is 82db and its bandwidth is 200MHz. Power consumption is one of the main design challenges in very-lowvoltage high-speed analog integrated circuits. In this paper, different techniques to reduce the power consumption in l...

Op-amp in loop filter While the cases using the passive loop filter (no op-amp) are simply a matter of circuit analysis, the case using the active filter requires some explanation. This case will only be described here; the accompanying analysis can be found in the supporting MathCad documents. With the op-amp in the loop, and the filter configuration shown in Figure 1, four different noise sou...

As device size scales down, there have been challenges to design conventional analog circuits, such as low voltage headroom and the low intrinsic gain of a device. Although ever-decreasing device channel length in CMOS technology has mainly negative effects on analog circuits, it increases device speed and reduces the power consumption of digital circuits. As a result, time-based signal process...

A High Swing Ultra-Low-Power Two Stage CMOS OP-AMP in 180 nm and 350nm Technology with 1.5V supply, is presented. Cascode technique has been used to increase the dc gain. The unity-gain bandwidth is also enhanced using a gain-stage in the Miller capacitor feedback path. It have 92.45 degree phase margin. The circuit has 94.866dB gain for 180nm. The power dissipation of the designed only is appr...

This paper describes the design of a high-speed CMOS sampleand-hold (S/H) circuit for pipelined analog-to-digital converters (ADCs). This S/H circuit consists of a switched-capacitor (SC) amplifier and a comparator to generate the mixed-mode sampled output data, which are represented both in analog and digital forms. The mixed-mode sampling technique reduces the operational amplifier (op amp) o...

In this paper the Darlington pair and internal circuit biasing technique is used for the enhancing the slew rate as well as gain and unity gain bandwidth. The proposed CMOS Op-Amp has been verified through Cadence Analog Design Environment with spectre simulator in the standard 45nm CMOS process. In this proposed circuit the gain stage is divided in two parts, first is modified gain stage and s...

Analog-to-digital converters provide a vital interface in mixed-signal electronic systems. One of the typical approaches to implement high-resolution sigma-delta modulators often involves the choice of high-order loop-filters, which imply the use of a large number of integrators. As in common topologies each integrator is implemented by one operational amplifier, high-order modulators can deman...