Optical transimpedance receivers implemented in CMOS VLSI technologies are modeled and optimized for freespace optoelectronic interconnections. Sensitivity, bandwidth, power dissipation, and circuit area are analyzed for receivers using three different submicron CMOS processes. A comparison with the circuit noise limited optical power indicates that, for digital computing applications, the rece...

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adde...

This paper presents a new CMOS buffer circuit topology for radiofrequency (RF) applications based on a fully-differential voltage-combiner circuit, capable of operating at low-voltage. The proposed circuit uses a combination of common-source (CS) and common-drain (CD) devices. The simulation results show good levels of linearity and bandwidth. To improve total harmonic distortion (THD) a source...

This paper describes a semi-dynamic CMOS flip-flop family featuring embedded Threshold Logic functions. First, we describe the new Threshold Logic flipflop concept and circuit operation. Second, we present the concepts of embedded Threshold logic and run-time reprogrammability. Finally, it is proved by Spice simulation results that wide (up to 8 inputs) AND/OR Boolean functions can be embedded ...

| With the growing scale of integration and the increased use of battery operated devices the power dissipation of CMOS circuits becomes an important factor in the design process. Power dissipation in CMOS-gates depends on the capacity switched and the transition density. Gate sizing is used to scale gates and their internal capacities. Smaller gates mean smaller capacities and therefore less p...

Now–a-days in digital circuits design high speed, high throughput, small silicon area, and at the same time, lowpower consumption of digital circuit is most important things for digital circuit designers. In this paper a novel design method of a low power digital circuit is discussed, where the GATE DIFFUSION INPUT (GDI) technique has been used for the simultaneous generation of digital logic f...

This paper presents logic style comparisons based on different logic functions and claimed modified Gate Diffusion Input logic (Mod-GDI) to be much more power-efficient than Gate Diffusion Input logic (GDI) and complementary CMOS logic design. However, DC and Transient analysis performed on more efficient modified Gate Diffusion Input logic (Mod-GDI) circuit realizations and a wider range of di...

| An 8 x 8-b nRERL serial multiplier is implemented in a 0.6m n-well 3-metal CMOS process. nRERL (nMOS Reversible Energy Recovery Logic) is a new reversible adiabatic logic circuit, which can be operated at the leakage-current level for ultralow-energy applications. Measurement results showed that the nRERL serial multiplier consumed only 0.9 % of the energy dissipation of the static CMOS one a...

Logic Delay Uncertainty Takashi Matsumoto Department of Communications and Computer Engineering Kyoto University, Kyoto, Japan Email: [email protected] Kazutoshi Kobayashi Department of Electronics Kyoto Institute of Technology, Kyoto, Japan Hidetoshi Onodera Department of Communications and Computer Engineering Kyoto University, Kyoto, Japan Abstract—Statistical nature of RTN-...

This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a highspeed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure ...