 Conventional PLL design techniques used to implement CMOS GHz range clock recovery circuits typically suffer from significant power supply coupled noise in large integrated systems. This noise worsens the jitter of the PLL and degrades the system Bit-ErrorRate (BER). This paper describes an analog approach which applies fully differential current steering technique throughout the whole PLL sy...

A 2-digit higher radix analog-to-digital converter (ADC) circuit consisting of a combination of a pipelined ADC and a set of cascaded current comparator cell has been proposed. The ADC generates multi-valued logic outputs rather than the conventional binary output system. The design is implemented using 0.25μm CMOS process. The performance analysis of the design shows desirable performance para...

With the dramatic increase in the number of transistors on a chip and the increasing needs for battery-powered applications, low-voltage circuit design techniques have been widely studied in recent year. However, these low supply voltage research efforts have been focused mainly on digital circuits, especially on high density memory circuits. Reported success in achieved high performance low vo...

A two-dimensional network for motion detection constructed of simple analog circuits was proposed and designed based on the frog visual system. In the frog visual system, the two-dimensional motion of a moving object can be detected by performing simple information processing in the tectum and thalamus of the frog brain. The measured results of the test chip fabricated by a 1.2 μm complementary...

We have designed, fabricated, and tested a series of compact CMOS integrated circuits that realize the winner-take-all function. These analog, continuous-time circuits use only O(n) of interconnect to perform this function. We have also modified the winner-take-all circuit, realizing a circuit that computes local nonlinear inhibition. Two general types of inhibition mediate activity in neural s...

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to ...

Here we describe a multi-compartment neuron circuit based on the Adaptive-Exponential I&F (AdEx) model, developed for the second-generation BrainScaleS hardware. Based on an existing modular Leaky Integrate-and-Fire (LIF) architecture designed in 65 nm CMOS, the circuit features exponential spike generation, neuronal adaptation, inter-compartmental connections as well as a conductance-based res...

A measurement method is proposed to characterize the substrate coupling between digital and analog sections of a mixed-signal CMOS chip. Induced noise and spurious signals can be measured by a custom-designed analog sensor. This paper proposes a method that, when given such a sensor, allows to measure the crosstalk between digital and analog chip sections. Calibrated sampling scope measurements...

This paper presents a monolithic optical detector, consisting of an integrated photodiode and a pre-amplifier in a standard 0.18μm CMOS technology. 3Gb/s data-rate was achieved at λ=850nm with an average optical power of 25 μW and BER10. This data-rate is over half an order of magnitude higher than that of current state-of-the-art optical detectors in standard CMOS. High speed operation is achi...