| In this paper, we present our datapath synthesis and layout tools which are targeted toward large-scale con gurable systems with the logic capacity of up to millions of gates which consists of an easy design entry using C++, customized bit-serial circuit library for SRAM-based FPGAs, bit-serial pipeline circuit generator, and a circuit partitioner.

Bit-serial architectures require less area but more sophisticated clocking mechanisms than their parallel counterparts. This paper presents a CMOS circuit that generates high-frequency clock waveforms for bitserial hardware. Triggered by a master clock input, the circuit outputs a fixed number of pulses followed by a completion signal. The design uses two coupled ring oscillators to produce dif...

In this paper, an analysis comparing the efficiency of different test strategies on a moderate complexity mixedsignal circuit is presented. Selected test strategies from the groups of functional, structural and parametric approaches were applied for the circuit test while considering bridging faults introduced into the circuit layout. The faults were extracted from the layout of the circuit. Fa...

"'.his paper describes thc algorithms. implementation, and performance of a hierarchical circuit extractorfor NMOS designs. The input to the circuit extractor is a description of the layout of the chip. and its outputis a hierarchical wirelist describing the circuit. The extractor is divided into two parts, a front-end and aback-end. The front-end analyzes the CIF description of...

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL's internal control voltage and output time delay. Circuit post-layout simulation shows ...

This paper presents the design, layout, and testability analysis of delay-insensitive circuits on cellular arrays for nanocomputing system design. In delay-insensitive circuits the delay on a signal path does not affect the correctness of circuit behavior. The combination of delayinsensitive circuit style and cellular arrays is a useful step to implement nanocomputing systems. In the approach p...

We describe a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks each with associated design knowledge. We also describe mechanisms to select from among alternate design styles, and to translate performance specifications from one level in the hierarchy to the next lower level. A prot...

A new method for designing single rail asynchronous circuits is studied. It utilises additional circuitry to monitor the activity of nodes within combinational logic blocks. When all transitions have halted a completion signal is generated. Details of the circuit and design methodology are given and the influence of glitches on the proposed circuit is discussed. Three different levels of granul...

We use evolutionary search to design combinational logic circuits which is based on evolving the functionality and connectivity of a rectangular array of logic cells in addition to the layout of this array. The evolutionary process contains two main steps. Initially the genome fitness in given by the percentage of output bits, which are correct. Once 100% functional circuits have been evolved, ...