Design and simulation of Digital PLL has been illustrated in this paper. The Digital PLL is given signal of 400 MHz to 900 MHz in the UNII (Unlicensed National Information Infrastructure) lower band which is used by IEEE 802.11(a). All the Digital PLL blocks are designed and simulated using Simulink. It is verified that Digital PLL is stable with a phase margin of 91.1 degree which satisfy the ...

The purpose of this study is to measure and compare the hemolysis produced by roller pumps with varied occlusion settings and a centrifugal pump. The null hypothesis is that there is no difference in the Index of Hemolysis (IH = gm Hb/100 L pumped) produced by a roller pump (RP) at four different occlusion settings and a centrifugal pump (CP) at the same blood flow rate (4.5 L/min) and afterloa...

Along with the System-on-Chip (SoC) concept being widely adopted, more and more building blocks are to be implemented into one chip. However, those different building blocks are generally not all specified with the same supply voltage, for example, 1.8V for the digital parts while 3.3V for the analog parts in most 0.18μm products. Generally, Low-Dropout (LDO) regulators are used to solve the pr...

Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump by the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-en...

New MOS charge pumps utilizing the charge transfer switches (CTS’s) to direct charge flow and generate boosted output voltage are described. Using the internal boosted voltage to backward control the CTS of a previous stage yields charge pumps that are suitable for low-voltage operation. Applying dynamic control to the CTS’s can eliminate the reverse charge sharing phenomenon and further improv...

In this letter, a new cross-coupled charge pump for negative high voltage generation has been proposed. The problem of shoot-through current in the conventional cross-coupled charge pump is solved by a four clock phase scheme. By switching the power supply to each stage based on the supply voltage, a variable voltage gain is obtained. A complete analysis of the interaction between the power eff...

A power management unit (PMU) is an essential block for diversified multi-functional low-power Internet of Things (IoT) and biomedical electronics. This paper includes a theoretical analysis high current, single-stage ac-dc, reconfigurable, dual output, regulating rectifier consisting pulse width modulation (PWM) frequency (PFM). The provides two independently regulated supply voltages 1.8 V 3....

In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...

Focusing on internal high-voltage ( ) switching and generation for low-voltage NAND flash memories, this paper describes a switch, row decoder, and charge-pump circuit. The proposed nMOS switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the leakage current. The proposed ro...