This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme for dynamic circuits provides the solution of the problem caused by logic polarity and clock skew problem simultaneously. To demonstrate the proposed clocking strategy, a 32 bit Carry Look Ahead adder (CLA) is designed a...

Flexibility and Portability has increased the requirement of Low Power components in fields like multimedia, signal processing and other computing applications. Adders are the essential computing elements in such applications. However the present adder architectures with hybrid/heterogeneous features provide performance variations but limits to consume less power. In this paper, low power heter...

Processor speed largely governed by the multiplier architectures. It is desired to have faster ALU with lower power consumption for portable applications to have good battery life. Hence, there is need to address different multiplier architectures. In this paper, the analysis of 4-bit multiplier using a Vedic Mathematics (Urdhva Tiryagbhyam sutra) and conventional multiplier with two different ...

This is an experimental article which shows that logical correctness of logic circuits can be easily proven by the Mizar system. First, we define the notion of logic gates. Then we prove that an MSB carry of ’4 Bit Carry Skip Adder’ is equivalent to an MSB carry of a normal 4 bit adder. In the last theorem, we show that outputs of the ’4 Bit Carry Look Ahead Adder’ are equivalent to the corresp...

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. The array multiplier and Braun array multipliers perform multiplication operation on unsigned numbers only. Thus, the requisite of the modern ...

To reduce power utilization and area are some of the most important criteria for the fabrication of Digital Signal Processing and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. In most of the multiplication, the multiplier is an energyhungry component. To improve energy efficiency of multipliers, the choice of multiplier is very important. Her...

Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family. Speedups of 2x10 3X over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic...

An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer. And it is a digital circuit comprised of the basic electronics components, which is used to perform various function of arithmetic and logic and integral operations further the purpose of this work is to propose the design of an 8-bit ALU which supports 4-bit multiplication. Thus, the ...

The fully Homomorphic encryption scheme is corner stone of privacy in an increasingly connected world. It allows to perform all kinds computations on encrypted data. Although, time bottleneck numerous applications real life. In this paper, a brief description made the homomorphic TFHE Illaria Chillota and others. TFHE, implemented c language library, improves bootstrapping execution FHEW 13 mil...

<span lang="EN-US">A new design of binary parallel adder circuit is presented in this paper. The pipeline technique applied to implement a group half (HA) blocks architect the proposed adder. pipelined carry (PCA) method suitable for carrying out desired by using HA circuits XOR and AND gates. reduces critical path delay 27% compared with ripple (RCA) relatively lowers logic gates 55% loo...