This paper presents a low complexity architecture for a linear periodically time varying (LPTV) filter. This architecture is based on multi-input multi-output(MIMO) representation of LPTV filters. The input signal is divided into blocks and parallel processing is incorporated, there by considerably reducing the effective input sampling rate. A single multiplier can be shared for each linear tim...

Abstract—In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35μm and 0.18μm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63% less than that of Braun array multiplier for 0.18μm t...

In many high speed Digital Signal Processing (DSP) and multimedia applications, the multiplier plays a very important role because it dominates the chip power consumption and operation speed. In DSP applications, in order to avoid infinite growth of multiplication bit width, it is necessary to reduce the number of multiplication products. Cutting off n-bit Less Significant Bit (LSB) output can ...

Galois field arithmetic is commonly used in Reed-Solomon encoding and decoding. This paper presents the design of a combined 16-bit binary and dual Galois field (GF) multiplier. This multiplier is capable of performing either a 16-bit two’s complement or unsigned multiplication, or two independent 8-bit GF(28) multiplications in SIMD fashion. The combined multiplier is designed by modifying a c...

Bit-sequential multiplier is being studied in a (+1, -1) binary representation. The maximum length of multiplier for a fix point numbers consists of n module. Each module is a five bit adder which contains 5 inputs and 3 outputs. It also contains an additional pin at the input as well as at the output. Computation time for multiplication is of the order of O(n). Hardware realization of module i...

A low latency digit serial multiplier for GF(2m) that can be pipelined to the bit-level is presented in this paper. Unlike existing structures, the new multiplier does not put any restriction on the type of generator polynomial used or the digit size. Furthermore, the latency of the new multiplier is significantly less than the latency of the existing bit-level pipelined digit-serial multiplier...

The performance of public-key cryptosystems like the RSA encryption scheme or the Diffie-Hellman key agreement scheme is primarily determined by an efficient implementation of the modular arithmetic. This paper presents the basic concepts and design considerations of the RSAγ crypto chip, a high-speed hardware accelerator for long integer modular exponentiation. The major design goal with the R...

Two novel neural chips SAND (Simple Applicable Neural Device) and SIOP (Serial Input Operating Parallel) are described. Both are highly usable for hardware triggers in particle physics. The chips are optimized for a high input data rate at a very low cost basis. The performance of a single SAND chip is 200 MOPS due to four parallel 16 bit multipliers and 40 bit adders working in one clock cycle...

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...