This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS...

T’fris paper introduces a two-port BiCMOS static memory cell that combines ECL-level word-linevoltageswingsandemitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access (CSEA) cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAM’S while preserving the high density and low power...

This communication describes the design of a microelectronic BiCMOS analog circuit, intended to be applied to the sliding-mode control of switching DC-DC power converters for the application of generating a sinusoidal signal with externally adjustable amplitude, frequency and offset. The circuit implements a sliding law over a nonlinear autonomous switching surface. The proposal of this analog ...

This paper presents a 20–32-GHz wideband BiCMOS mixer with an IF bandwidth of 12 GHz. The mixer utilizes an inductive peaking technique to extend the bandwidth of the downconverted IF signal. To our knowledge, the proposed mixer achieves the widest IF bandwidth using silicon-based technologies in -band. Analytical expressions for the conversion gain and output noise of the proposed mixer are pr...

This paper discusses design issues for high-performance BiCMOS output buffers, as required in T&Hs and data converters for advanced applications. We compare different topologies and analyze the main limitations. The best solution features a linearity better than -105 dB (HD3) at an input frequency of 100 MHz. The simulation results referred to a conventional 0.8 pm BiCMOS process cover a huge r...

This paper describes the first integrated transversal filter for feed-forward equalizers (FFE) operating above 40 Gb/s. Equalization of a 2−1 PRBS over a 9-ft and 6.5-ft cable with SMA connectors is demonstrated on-wafer at 40 Gb/s and 49 Gb/s respectively. The circuit is implemented in a commercial 0.18 μm SiGe BiCMOS process and is based on a differential distributed 7-tap fractionally spaced...

This paper presents an 8-18GHz wideband receiver with superheterodyne topology. In order to save power, both RF and IF signals share the tunable transconductance stage. The IF output of the first mixer is fed to its tunable input stage for IF amplification in a recursive manner, which significantly enhances the gain tuning without increasing the power. The wideband receiver MMIC is implemented ...

In BiCMOS, transi s t or s t uck-OPEN fault s exhi bi t del ay f aul t s i n addi t i on t o s equent i al behavi or . St uckON f aul t s caus e enhanced I DDQ. The f aul t y behavi or of Bi pol ar (TTL) and CMOS l ogi c f ami l i es i s compar ed wi t h Bi CMOS. The f aul t s i n Bi CMOS devi ces caus e one or more par t s ( ppar t or npar t s ) of t he ci r cui t t o ex hi bi t a di er ent s ...

This paper presents a fully integrated 5.4-GHz CMOS Voltage-controlled Oscillator (VCO) with a low phase noise and ultra linear VCO gain (Kvco) in 0.35-μm SiGe (Silicon Germanium) BiCMOS technology. In order to increase the linearity of the VCO, a resonant circuit is proposed that consists of four parallel p-n junction varactor pairs. The VCO operate at a bias current of 3.13 mA and a supply vo...