A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a given fault model. The approach is based on decomposition of functional memory faults into basic fault effects and output tracing. Output tracing involves storing all read operation results for defective memory cells and r...

A deterministic dynamic element matching (DEM) approach to ADC testing is introduced and compared with a common random DEM method. With both approaches, a highly non-ideal DAC is used to generate an excitation for a DUT that has linearity that far exceeds that of the test stimulus. Simulation results show that both methods can be used for testing of ADCs but with a substantial reduction in the ...

The design and architecture of a reconngurable memory BIST unit is presented. The proposed memory BIST unit could accommodate changes in the test algorithm with no impact to the hardware. Diierent types of march test algorithms could be realized using the proposed memory BIST unit and the proposed architecture allows addition and elimination of the memory BIST components. Therefore memories wit...

When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the seria...

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In this paper, we present a BIST technique that measures the RMS value of a Gaussian distribution period jitter. In the proposed approach, the signal under test is delayed by two different delay values and the probabilities it leads the two delayed signals are measured. The RMS jitter can then be derived from the probabilities and the delay values. Behavior and circuit simulations are performed...

Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes perform testing concurrently with the operation of the circuit. In this paper a novel input vector monitoring concurrent BIST scheme is presented that compares favorably to previously proposed schemes with respe...