We use hedonic analysis of home transaction data from the Minneapolis–St. Paul metropolitan area to estimate the effects of proximity to open space on sales price. We allow the effects of proximity to vary with demographic and location-specific characteristics and include fixed effects to control for observed and unobserved neighborhood characteristics. We find that the value of proximity to op...

Coarse-grained reconfigurable arrays, or CGRAs in short, have drawn increasing attention recently due to their performance and flexibility. They provide flexibility through reconfiguration, which is not attained with fixed harware such as traditional ASICs. They also provide performance through highly parallel architecture, which is hardly achieved with basically sequential software running on ...

In sub-micron processes, resistive path defects are increasingly contributing to the yield loss and the customer fail pareto. Data has been collected on a series of ASIC products and compares the effectiveness of full vector set transition delay fault tests with reduced vector sets, minVDD, customer functional tests and customers system fails. Results show that fault models do not predict the d...

This paper presents a new feature point detector that is accurate, efficient and fast. A detailed qualitative evaluation of the proposed feature point detector for grayscale images is also done. Experiments have proved that this feature point detector is robust to affine transformations, noise and perspective deformations. More over the proposed detector requires only 22 additions per pixel to ...

The field of lightweight cryptography has developed significantly over recent years and many impressive implementation results have been published. However these results are often concerned with a core computation and when it comes to a real implementation there can be significant hidden overheads. In this paper we consider the case of cryptoGPS and we outline a full implementation that has bee...

A demonstrator for OFDM transmission based on a programmable DSP (TMS320C6201) is described. It turns out that the realized rather moderate sampling rates up to 10 Msamples/s still represent quite a challenge for state-of-the-art DSPs in terms of the required computational power but also the synchronization of the internal processing with the I/O interface to a real-time environment. It is illu...

A high-performance ASIC has been developed to serve as the interface for the 10-ns bus in the new AlphaServer 8000 series server systems from Digital. The CMOS standard-cell alternative (CSALT) technology provides a timing-driven layout methodology together with a correct-by-construction approach for managing the complex device physics issues associated with state-of-the-art CMOS processes. The...

This paper presents a French public programme set up in order to assist small and medium-sized industries that are willing to implement ASICs or new electronic technologies in their products. After the presentation of the general frame of this programme, the specific actions will be detailed: SMIs awareness to new technologies, and specialised training sessions in microelectronics that were def...

xiv

Complex integrated systems contain more and more on-chip components which exchange data and access memories via buses. To consider parasitic effects on bus structures during the early design phase appropriate models and wiring methods must be available. A RC-Pi model is proposed to model the load of a bus driver cell that also considers capacitive coupling between the signal lines. On the basis...