This paper describes the architecture and the IC implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm (similar to CORDIC). It is shown that the architecture can be implemented as a multiplierless, feedforward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 1.0m CMOS, and tested. The IC produces 16-b sine ...

ABSTRACT In this thesis, a method of time-interleaving continuous-time delta-sigma modulators is investigated. The derivation of the modulator starting from a discrete-time timeinterleaved structure is presented. With various simplifications, the resulting modulator has only a single-path of integrators, making it robust to DC offsets. A third-order lowpass continuous-time time-interleaved delt...

We describe efficient four-coil inductive power transfer (IPT) systems that operate at 100 MHz. The magnetically coupled transmitter and receiver were made from electrically small high- Q loop-gap resonators (LGRs). In contrast to the commonly used helical spiral resonators, LGR design has distinct advantage electric fields are strongly confined capacitive gap of resonator. With negligible frin...

in this paper, a low voltage and low power (lv/lp) operational transconductance amplifier (ota) using fgmos (floating-gate mos) transistor is proposed. the relative tuning range of 50 is achieved in this ota while only consumes 40 µw with 1.0 v supply voltage in tsmc 0.18 µm cmos technology. the simulation results of the proposed ota show an open loop gain of 30.2 db and a unity gain frequency ...

It is desirable to develop rapid commercial microwave and radio frequency sterilization processes to produce high quality shelf stable muscle foods, particularly aquatic foods. Whey protein gels containing D-ribose and salt were studied as a model food to determine heating patterns in salmon fillets during high temperature microwave sterilization processes. Dielectric constant (30) and loss fac...

A new feed system is designed for the Expanded Very Large Array (EVLA) for operation below 100 MHz. The only existing system on the EVLA operating below 100 MHz is the “4 m” (74 MHz) system which uses crossed half-wave dipoles located in front of the Cassegrain subreflector as the feed. However, the dipole feeds of this system introduce blockage, and a reduction in system sensitivity (estimated...

PLLs (phase-locked loops) are common analog circuits in SOCs (systems on chips). Almost all SOCs with a clock rate greater than 30 MHz use a PLL for frequency synthesis. However, a “one-size-fis-all” PLL does not exist. The devices have a range of frequency, power, area, performance, and functions. PLLs implemented in 100 nm or smaller processes typically range in frequency from 10 MHz to 10 GH...