Substantial increase in gate and sub-threshold leakage of complementary metal-oxide-semiconductor (CMOS) devices is making it extremely challenging to achieve energy-efficient designs while continuing their scaling at the same pace as in the past few decades. Designers constantly sacrifice higher levels of performance to limit the ever-increasing leakage power consumption. One possible solution...

A new continuous-time CMOS current comparator having high speed and low power is proposed as an important component of current mode signal processing unit. It comprises of CMOS complementary amplifier with a feedback MOS resistor, two resistive load amplifiers and two CMOS inverters. Short response delay, low power consumption and small area are some of its features. Due to the absence of bias ...

The complementary M-ary orthogonal spreading with frequency division multiplexing (CMOS-OFDM) is an efficient scheme for providing high bit error rate (BER) performance and low peak to mean envelop power ratio (PMEPR) in (HF) communications system. In the CMOS-OFDM, OFDM implemented based on sequence pairs where there issue that one data symbol transmitted through two symbols. this paper, we pr...

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed a...

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compati...

Requirements of RF CMOS device and its related design issues to operate at high frequencies are discussed. Problems faced by current CMOS models and its lack of accuracy in capturing high frequency are focused. To improve model accuracy, Vendor modeling approach is discussed to model frequency dependent parameters like substrate resistance, gate resistance and noise signals. In this connection,...

A new CMOS-based image sensor that is intrinsically compatible with onchip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 pm p-well CMOS process, and consists of a 128 x 128 array of 40 pm x 40 pm pixels. The CMOS image sensor technology ena...

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design which adopts gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals, then a clocked CMOS gate structure is presented. The PSPICE simulations demonstrate the low power characteristic of clocked CMO...