This paper presents a formal model of several fundamental concepts in VHDL including the semantics of individual concurrent statements, and groups of those statements, resolution functions, delta delays, and hierarchical component structuring. Based on this model, several extensions to VHDL are proposed, including nondeterministic assignments and unbounded asynchrony. Nondeterminism allows the ...

Relating to a previous simplified VHDL processor model [1], a more advanced synthesized VHDL pipeline microprocessor model was developed and has been used in the second term computer architecture course offered in the School of Electrical and Computer Engineering at the Georgia Institute of Techonology. This paper will first describe the pipeline processor model and its VHDL implementation. The...

Fault injection provides a method of assessing the dependability of a system under test. Traditionally fault injection is employed near the end of the design process after hardware and software prototypes have been developed. In order to eliminate costly re-designs near the end of the design process, a methodology for performing fault injection throughout the design process is described in this...

The introduction of HDLs (hardware description languages) have made a significant contribution to VLSI circuit design. While these languages are well suited to describe circuits in great detail, they are found wanting when attempting formal verification of circuits. One of the drawbacks lies in the lack of formal models of semantics. VHDL, with a wide variety of tools available to carry out cir...

Ultracentrifugally isolated high density lipoprotein (HDL) particles of d greater than 1.125 g/ml promote net transport of cholesterol from cultured cells. Consequently, when cultured human fibroblasts and arterial smooth muscle cells were incubated with HDL3 (d = 1.125-1.21 g/ml) and "very high" density lipoprotein (VHDL, d = 1.21-1.25 g/ml), low density lipoprotein (LDL) receptor activity was...

.............................................................................................................................. I TABLE OF CONTENTS............................................................................................................ I LIST OF FIGURES................................................................................................................. IV LIST OF ...

As embedded systems are becoming increasingly complex, the design process and verification have become very time-consuming. Additionally, specifying hardware manually in a low-level hardware description language like VHDL is usually an error-prone task. In our group, a tool (the CλaSH compiler) was developed to generate fully synthesisable VHDL code from a specification given in the functional ...

The underlying nature of adiabatic circuits is most accurately characterized at the circuit level as it for traditional technologies. In order to scale system designs logic technologies, modeling necessary. Logic models can facilitate design, development, and verification large digital systems that may be infeasible using simulators. Adiabatic powered with a four stage power clock consisting id...

UT Mixed-Signal Simulator is a mixed-signal, mixeddomain, and mixed-language design environment which supports VHDL-AMS 1999, VHDL-2002, Verilog 2001, SystemVerilog 2005 assertions, and SystemC 2005.

This paper provides an overview of the VHDL AMS hardware description language for analog and mixedsignal applications like the switched mode power supply which is designed by describing the major elements or components of the system with the help of this hardware descriptive language and illustrating it using Hamster which is a simulation software for VHDL and Verilog Descriptive Language. Inde...