We report an SRAM with a 90% reduction of activeleakage power achieved by controlling the supply voltage. In our design, the supply voltage of a selected row in the SRAM goes up to 1 V, while that in other memory cells that are not selected is kept at 0.3 V. This suppresses active leakage because of the drain-induced barrier lowering (DIBL) effect. To avoid unexpected flips in the memory cells,...

The SRAM (static random access memory) extensively used in computers, embedding hardware, and other digital systems is a main source of power dissipations. In order to reduce the increasing power dissipation of the SRAM, a low-power adiabatic SRAM is introduced. The proposed SRAM is realized by PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) to reduce its dynamic ener...

In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The H...

In sub-100 nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local DC level control (LDLC) for static random access memory (SRAM) cell arrays and an automatic gate leakage suppression drive...

A SRAM cell must meet requirements for operation in submicron. As the density of SRAM increases, the leakage power has become a significant component in chip design. The power Consumption is a major issue of today's CMOS Technology. Leakage power is major issue for short channel devices. As the technology is shrinking the leakage current is increasing very fast. so, several methods and techniqu...

This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the c...

To reduce the dynamic power consumption in SRAM a new design technique is proposed here. The proposed technique is compared with 8T SRAM cell design technique using 0.18 micron technology. Simulation results indicates that the proposed technique provides an improvement of 64% in bitline leakage ,22.64% in write ‘0’ power, 30.68% in write ‘1’ power over 8T SRAM cell design technique.

A physical unclonable function (PUF), analogous to a human fingerprint, has gained an enormous amount of attention from both academia and industry. SRAM PUF is among one of the popular silicon PUF constructions that exploits random initial power-up states from SRAM cells to extract hardware intrinsic secrets for identification and key generation applications. The advantage of SRAM PUFs is that ...

In energy-aware design, especially for systems with uncertain power sources, asynchronous computation loads which can function under variable power supply have many potential advantages. Fully safe asynchronous loads based on delay insensitivity (DI), however, tend to suffer power and size penalties. As a compromise, delay bundling has been widely used in asynchronous computation, but tradition...