Human VRK1 induces a stabilization and accumulation of p53 by specific phosphorylation in Thr18. This p53 accumulation is reversed by its downregulation mediated by Hdm2, requiring a dephosphorylated p53 and therefore also needs the removal of VRK1 as stabilizer. This process requires export of VRK1 to the cytosol and is inhibited by leptomycin B. We have identified that downregulation of VRK1 ...

In modern processors, the DRAM system is shared among concurrently-executing threads. Memory requests from a thread can delay requests from other threads by causing bank/bus/rowbuffer conflicts. Conventional DRAM controllers are unaware of inter-thread interference, which causes two problems. First, some threads are unfairly penalized and denied DRAM service for long time periods. Second, as we...

Abstract As process technology scales, the number of transistors that can fit in a unit area has increased exponentially. Processor throughput, memory storage, and memory throughput have all been increasing at an exponential pace. As such, DRAM has become an ever-tightening bottleneck for applications with irregular memory access patterns. Computer architects in industry sometimes use ad hoc an...

The demand for accurate information about the internal structure and characteristics of dynamic random-access memory (DRAM) has been on rise. Recent studies have explored DRAM to improve processing in memory, enhance reliability, mitigate a vulnerability known as rowhammer. However, manufacturers only disclose limited through official documents, making it difficult find specific actual devices....

Recent developments in the theory of DRAM fault modeling have identified the space of tests needed to detect all DRAM faults. Tests developed to target transient DRAM faults are very time consuming, as they have a quadratic dependence on the number of tested memory cells. This paper presents techniques to reduce the complexity of these tests. The paper also introduces a reduced test, with linea...

As process technology scales down to smaller dimensions, DRAM chips become more vulnerable to disturbance, a phenomenon in which different DRAM cells interfere with each other’s operation. For the first time in academic literature, our ISCA paper [21] exposes the existence of disturbance errors in commodity DRAM chips that are sold and used today. We show that repeatedly reading from the same a...

Performance improvements from DRAM technology scaling have been lagging behind the improvements from logic technology scaling for many years. As application demand for main memory continues to grow, DRAM-based main memory is increasingly becoming a larger system bottleneck in terms of both performance and energy consumption. A major reason for poor memory performance and energy efficiency is me...

A Physically Unclonable Function (PUF) is a unique and stable physical characteristic of a piece of hardware, due to variations in the fabrication processes. Prior works have demonstrated that PUFs are a promising cryptographic primitive to enable hardware-based device authentication and identification. A diverse number of PUFs have been explored, e.g., delay-based PUFs in dedicated circuits, S...

With the imminent slowing down of DRAM scaling, Phase Change Memory (PCM) is emerging as a lead alternative for main memory technology. While PCM achieves low energy due to various technology-specific advantages, PCM is significantly slower than DRAM (especially for writes) and can endure far fewer writes before wearing out. Previous work has proposed to use a large, DRAM-based hardware cache t...

A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integrates four processing elements, a total of 16 Mbit DRAM, and application specific interfaces. A hierarchical test strategy has been developed to test the different structures of the system such as processing elements an...