This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshakecomponent-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an areaefficient architecture of an FPGA that is suitable for handshake-componentbased asynchronous circuit. Moreover, the Four-Phase Dual-Rail en...

Self-Timed FPGA Systems p. 21 XC6200 Fastmap Processor Interface p. 36 The Teramac Configurable Computer Engine p. 44 Telecommunication-Oriented FPGA and Dedicated CAD System p. 54 A Configurable Logic Processor for Machine Vision p. 68 Extending DSP-Boards with FPGA-Based Structures of Interconnection p. 78 High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform ...

system has very much importance because it will increase performance and accuracy. The fault injection method is used to find out the fault tolerance of a system. This method is valuable and attractive. In this paper fast FPGA based fault injector for memory unit is introduced. In previous FPGA based fault injection methods the response according to the fault injection is send to the observatio...

Digital signal processing (DSP) occurs in communications, audio, multimedia devices, imaging and medical equipment, smart antennas, automotive electronics, MP3 players, radar and sonar, and barcode readers. This algorithm can be implemented in Microsemi® system-on-chip (SoC) Products Group flash based field programmable gate array (FPGA), mixed signals FPGA, and also radiation-tolerant FPGA. Th...

El objetivo de este trabajo fue evaluar el rendimiento las arquitecturas hardware: Hard Processor System (HPS) y la unión un HPS con una matriz compuertas programables o FPGA (HPS + FPGA) para sistema procesamiento imágenes. Se evalúan: tiempo ejecución los algoritmos imágenes consumo energía. Para Plataforma SoC se realiza diseño hardware en Verilog utilizando núcleos video IP del University P...

Recent advances in FPGA technologies allow to configure the RAM-based FPGA devices in a reduced time as an effective support for real-time applications. The physical dimensions of FPGAs (pinout and gate count) limit the complexity of circuits that can be implemented. In many applications, very large circuits should be realized without requiring either a very large FPGA or many FPGAs; in some re...

This paper describes the implementation and the performance analysis of a hardware accelerator for the BLAS library matrix multiplication operation. This accelerator is based on a dual-FPGA board and on an implementation BLAS software library making use of the FPGA-based hardware. In order to evaluate the performance of such a system, we implemented the matrix multiplication operation (BLAS “dg...

This paper presents a novel eld-programmable gate array logic block architecture which incorporates support for digit-serial DSP architectures on a digit wide basis, without diminishing the support for random and control logic applications. To eeciently realize a digit-serial DSP design on FPGAs, one must create an FPGA architecture optimized for those types of systems. Key to the suitability o...

We describe an FPGA accelerator for the Kannan–Fincke– Pohst enumeration algorithm (KFP) solving the Shortest Lattice Vector Problem (SVP). This is the first FPGA implementation of KFP specifically targeting cryptographically relevant dimensions. In order to optimize this implementation, we theoretically and experimentally study several facets of KFP, including its efficient parallelization and...