We present parallel algorithms and array architectures for pyramid vector quantization (PVQ) 3] for use in image coding in low-power wireless systems. Both encoding and decoding algorithms have data-dependent iteration bounds and data-dependent dependencies which prevent eecient parallelization of the algorithms. We perform an algorithmic transformation 4] to convert data-dependent regular algo...

This report aims at depicting the scenario of Network-On-Chip (NoC) architectures proposed from both academic institutes and industry. A review of suitable NoC simulators is presented, with the aim of having appropriate tool for an accurate evaluation of architectures and protocols performances on different application-domains. This is important when comparing NoC with traditional communication...

Biological systems routinely perform computations, such as speech recognition and the calculation of visual motion, that baffle our most powerful computers. Analog very large-scale integrated (VLSI) technology allows us not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI techno...

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The objective of this work is to develop discrete-time demodulator architectures for broadband optical pulse-position modulation (PPM) that are capable of processing Nyquist or near-Nyquist data rates. These architectures are motivated by the numerous advantages of realizing communications demodulators in digital very large scale integrated (VLSI) circuits. The architectures are developed withi...

In this paper, a real-time wavelet image compression algorithm using vector quantization and its VLSI architecture are proposed. The proposed zerotree wavelet vector quantization (WVQ) algorithm focuses on the problem of how to reduce the computation time to encode wavelet images with high coding efficiency. A conventional wavelet image-compression algorithm exploits the tree structure of wavel...

In this paper, five new multiplexer-based architectures for 1 -bit full adder circuit designs are proposed. Following these architectures, various full adder circuits can be built through different circuit implementations of multiplexers. For instance, in this paper, we demonstrate that by substituting each multiplexer with two transmission gates, a set of new full adder circuits are ready to b...

ÐThis paper presents a modular algorithm which is suitable for computing a large class of multidimensional transforms in a general purpose parallel environment without interprocessor communication. Since it is based on matrix-vector multiplication, it does not impose restrictions on the size of the input data as many existing algorithms do. The method is fully general since it does not depend o...

This chapter describes the main architectures proposed in the literature to implement the channel decoders required by the WiMax standard, namely convolutional codes, turbo codes (both block and convolutional) and LDPC. Then it shows a complete design of a convolutional turbo code encoder/decoder system for WiMax.

In this paper, we pursue the use of probabilistic (randomized) algorithms in VLSI architectures, in order to reduce the amount of computation, and, correspondingly, the time of computation as well as chip area. As a case example, we propose two VLSI solutions to the well-known problem of the nearest pair of points in computational geometry. These implementations are based on Rabin's and Weide's...