In digital signal processing convolution is a fundamental computation that is ubiquitous in many application areas. In order to compute convolution of long sequence, Overlap-Add method (OLA) and Overlap-Save method (OLS) methods are employed. In this paper, block convolution process is proposed using a multiplier architecture based on vertical and crosswise algorithm of Ancient Indian Vedic Mat...

In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per The proposed architecture, for two 8-bit numbers; th...

In this paper VHDL implementation of complex number multiplier using ancient Vedic mathematics and conventional modified Booth algorithm is presented and compared. The idea for designing the multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplicatio...

This paper proposes the hardware implementation of RSA encryption/decryption algorithm using the algorithms of Ancient Indian Vedic Mathematics that have been modified to improve performance. The recently proposed hierarchical overlay multiplier architecture is used in the RSA circuitry for multiplication operation. The most significant aspect of the paper is the development of a division archi...

Mathematics represents a high level of abstraction attained by the human mind. In India, Mathematics has its roots in Vedic literature which is nearly 4000 years old. Between 1000 B.C. and 1000 A.D. various treatises on Mathematics were authored by Indian mathematicians in which were set forth for the first time, the concept of zero, the techniques of Algebra and algorithm, square root and cube...

this paper portrays for the design of an area efficient 4×4 Vedic Multiplier by using Vedic Mathematics algorithms. Out of the 16 sutras the Urdhva -Tiryakbhyam sutra is being discussed and implemented because this sutra is applicable to all cases of algorithm for n×n bit numbers and gives minimum delay for multiplication of all types of numbers. The complete multiplier is designed using VHDL l...

This paper presents VLSI architecture for lifting based 2D DWT architecture with reduced delay. The proposed structure offers high speed and high area efficiency. Fast computation is achieved by replacing conventional multiplier units of DWT architecture with Vedic multiplier. Three sutras of Vedic multiplication are employed to reduce logic shifting operations of multiplier units and so high s...

Vedic mathematics is the system of mathematics followed in ancient Indian and it is applied in various mathematical branches. The word “Vedic” represents the storehouse of all knowledge. Because using Vedic Mathematics, the arithmetical problems are solved easily. The mathematical algorithms are formed from 16 sutras and 13 up-sutras. But there are some limitations in each sutra. Here, two sutr...

This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Triyagbhyam– Vedic method for multiplication which strikes a diff...