The paper is focused on the optimization and implementation of fully digital feed-forward blind oversampling CDR (BO-CDR). Two new phase-decision algorithms are proposed. Their complexity is very low, enabling a very simple and fast implementation even in FPGA, which was used as a development platform as well as a target device for the BO-CDR block. The FPGA-based optimization gave the opportun...

In this paper an efficient design and implementation of ITU-R BT.601 video filter has been presented for digital television receivers. The proposed video filter has been realized using MAC algorithm. The implementation is based on efficient utilization of embedded multipliers and look up table (LUT) of the target device to improve speed, area efficiency and power consumption. It is an efficient...

FPGA-based Genetic Algorithms (GAs) can effectively optimise complex applications, but require extensive hardware architecture customisation. To promote these accelerated GAs to potential users without hardware design experience, this paper proposes an automated framework for creating and executing a general-purpose GA system on FPGAs. This framework is a scalable and customisable hardware arch...

This article presents an architecture based on FPGA for the calculation of texture attributes using an adequacy of the technique of sum and differences of histograms. The attributes calculated by this architecture will be used in a process of classification for identification of objects during the navigation of an autonomous robot of service. Because of that, the constraint of real-time executi...

This paper describes design decisions for JOP, a Java Optimized Processor, implemented in an FPGA. FPGA density-price relationship makes it now possible to consider them not only for prototyping of processor designs but also as final implementation technology. However, using an FPGA as target platform for a processor different constraints influence the CPU architecture. Digital building blocks ...

FPGAs are well accepted as an alternative to ASICs and for rapid prototyping purposes. Netlists of designs which are too large to be implemented on a single FPGA, have to be mapped onto a set of FPGAs, which could be organized on an FPGA board containing various FPGAs connected by interconnection networks. This paper presents an efficient approach to the problem of multiway partitioning of larg...