A way to accelerate DEM calculations on the GPUs is developed. We examined how warp divergences take place in the contact detection and the force calculations taking account of the GPU architecture. Then we showed a strategy to reduce the impact of the warp divergences on the runtime of the DEM force calculations.

Systolic array designs are presented for decimation lters with an in nite input signal. The rst design is based on an existing design for convolution and is shown to be time optimal with respect to our criteria. Two new designs are derived by reducing the number of processing cells to the theoretical minimum while retaining optimal timing. EDICS number SP 5.1.4.

New systolic array based architecture for variable block size motion estimation is presented in this paper. The proposed architecture is scalable for various block sizes. High speed systolic array is designed for Sum of absolute difference (SAD) calculation of 4x4 block sizes. High speed is achieved by group 4 pixels into a single large pixel as sad’s can be calculated simultaneously for all th...

The paper presents the design of a hardware genetic algorithm which uses a pipeline of systolic arrays. Demostrated is the design methodology, where a simple genetic algorithm expressed in C source code is progressivly re-written into a recurrence form from which systolic structures can be deduced. The paper extends previous work by the authors by introducing a simplification to a previous syst...

In an earlier paper, an approximate SVD updating scheme has been derived as an interlacing of a QR updating on the one hand and a Jacobi-type SVD procedure on the other hand, possibly supplemented with a certain re-orthogonalization scheme. In this paper, this updating algorithm is mapped onto a systolic array with O(n 2 ) parallelism for O(n 2 ) complexity, resulting in an O(n 0 ) throughput. ...

Genetic Algorithms (GAs) are commonly used search algorithms and there is an incentive in accelerate their execution speed using hardware. We present a collection of systolic array designs which perform the Selection, Crossover and Mutation operations of the GA. Although the premise there is considerable generality in the genetic operators is true, it is accepted that GAs often use di erent tec...

Matrices have been used in many analytical and simulation models and numerical solutions. Matrix operations have essential role in many scientific and engineering applications. One of the most time-consuming operations among matrix operations is matrix inversion. Many hardware designs and software algorithms have been proposed to reduce the time of computation. They will be more important for t...

A design of systolic array-based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module...

Systolic arrays are a family of parallel computer architectures capable of using a very large number of processors simultaneously for important computations in applications such as scientific computing and signal processing. A discrete cosine transform (DCT) expresses a sequence of finitely many data points in terms of a sum of cosine functions at different frequencies. DCT is a Fourier-related...

We present a new algorithm and systolic array for adaptive beamforming. Our approach improves on McWhirter's pioneering work in two respects. First, our algorithm uses only orthogonal transformations and this should have better numerical properties. Second, the algorithms can be implemented on one single pxp triangular array of programmable processors that offers a throughput of one residual el...