Computer simulations needed by the U.S. Department of Energy (DOE) greatly exceed the capacity of the world’s most powerful supercomputers. To satisfy this need, the DOE created the Accelerated Strategic Computing Initiative (ASCI). This program accelerates the development of new scalable supercomputers and will lead to a supercomputer early in the next century that can run at a rate of 100 tri...

IEEE P1596, the Scalable Coherent Interface (formerly krrown as SuperBus) is based on experience gained while developing Fastbus (ANSI/IEEE 960-1986, IEC 935), Futurebus (IEEE P896.x) and other modem 32-bit buses. SC1 goals include a minimum bandwidth of 1 GByte/sec per processor in multiprocessor systems with thousands of processors; efficient support of a coherent distributed-cache image of d...

This work outlines the architecture and main features of the BESM-6 computer and data processing system AS-6. It also discusses the development of the “Electronika SS BIS-1” supercomputer system as well as the principle results of the research on multi-architecture (heterogeneous) supercomputer systems.

The absence of agreed definitions and metrics for supercomputer RAS obscures meaningful discussion of the issues involved and hinders their solution. This paper seeks to foster a common basis for communication about supercomputer RAS, by proposing a system state model, definitions, and measurements. These are modeled after the SEMI-E10 [1] specification which is widely used in the semiconductor...