AbstructA direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area. Analytical formulation for the pow...

As transistors continue to scale down into the nanometer regime,device leakage currents are becoming the dominant cause of powerdissipation in nanometer caches, making it essential to model theseleakage effects properly. Moreover, typical microprocessor cachesare pipelined to keep up with the speed of the processor, and theeffects of pipelining overhead need to be proper...

iii The portable communications industry's vision of integrating a complete multimedia complex on a single die, coupled with the desktop computing industry's vision of integrating multimedia functionality into general-purpose microprocessors has transformed lowering the power dissipation of digital signal processing (DSP) datapath circuits into an increasingly important challenge in current and...

Power dissipation is one of the critical design factors in microelectronics industry which opens lot of space for advance development in deep sub micron fabrication techniques for the devices. Low power design reduces cooling cost and increases reliability, especially for high density systems. Moreover, it reduces the weight and size of portable devices. In order to achieve the aim, static and ...

Presented in this paper is a fundamental mathematical basis for power-reduction in VLSI systems. This basis is employed to 1.) derive lower bounds on the power dissipation in digital systems and 2.) unify existing power-reduction techniques under a common framework. The proposed basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed...

experiments were carried out to observe the influence of loading type on concrete beam specimens. beam specimens made of similar concrete mixture with the same geometry were tested under three point static loading and low velocity drop weight impact loading. load – displacement behavior, absorbed energy dissipation capacity, stiffnesses, failure modes of beam specimens were obtained and discuss...

Presented in this paper is a fundamental mathematical basis for power-reduction in VLSI systems. This basis is employed to 1.) derive lower bounds on the power dissipation in digital systems and 2.) unify existing power-reduction techniques under a common framework. The proposed basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed...

We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal—oxide—semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can re...

The most research on the power consumption of 6T SRAM has been focused on the static power dissipation and the power dissipated by the leakage current. On the other hand, as the current VLSI technology scaled down, the sub-threshold current increases which further increases the power consumption. In this paper we have proposed 6T (8 X 8) SRAM cells using MCML technology which will reduce the le...

This paper describes an experimental chip of self-timed (clockless) power-aware pipeline incorporating stage-by-stage power gating scheme. Its power gating circuit cuts the voltage-supply to the idle pipeline stages in order to reduce the static (leakage) power dissipation. To reduce the dynamic power dissipation, self-timed pipeline (STP) is one of the suitable circuit architectures because it...