In this paper, the nearly instantaneous response of the seriesconnected VSC-based FACTS controllers when used to limit possible fault currents in a compensated line, will be presented. The effectiveness of both FACTS controllers (SSSC and UPFC) towards this system condition was investigated exploring the series voltage effect upon the line. Moreover, it will be shown that the UPFC shunt convert...

ObjectStab is a general purpose simulation tool for power system stability studies developed by Modelica which is an object-oriented modeling language. It provides enough modeling flexibility to allow addition or modification of new power system components. This paper describes an incorporated use of fuzzy logic toolbox in Matlab/Simulink and ObjectStab library to enhance the application of thi...

This paper proposes designing of Static Synchronous Series Compensator (SSSC) based damping controller to enhance the stability of a Single Machine Infinite Bus (SMIB) system by means of Invasive Weed Optimization (IWO) technique. Conventional PI controller is used as the SSSC damping controller which takes rotor speed deviation as the input. The damping controller parameters are tuned based on...

In recent years, various heuristic optimization methods have been developed. Many of these methods are inspired by swarm behaviors in nature. In this paper, a new optimization algorithm namely Gravitational Search Algorithm (GSA) based on the law of gravity and mass interactions is illustrated for designing Static Synchronous Series Compensator (SSSC) for single and multimachine power systems. ...

Improving transmission lines (TL) steady-state stability limit can be achieved by Static Synchronous Series Compensators (SSSC) that work as a converter-based compensator. The modification of the SSSC function to inject both active and reactive power into TL improves its performance according different indices. improvement indices include reduction losses, enhancement dynamic margin voltage pro...

??1? An engineering oriented approach for the design of selfsynchronizing stream ciphers is given. To show that it is useful in practice, an actual design is presented and motivated. This SSSC is claimed to be fast (gate delay 2 XORs), cryptographically secure and easily implementable in hardware (standard cells).