A 4 order RF LC Σ∆ ADC clocked at 3.6GHz and centered at 900MHz is presented. The simplicity of the ADC architecture results in a significant performance enhancement and power consumption reduction. The ADC, suitable for Software Defined Radio applications, is implemented in a standard 130nm CMOS technology. It achieves a 52dB SFDR and a 50dB SNDR in a 28MHz BW and consumes only 15mW from a 1.2...