OSPF, or Open Shortest Path First, is a commonly used interior gateway protocol. An integer weight is assigned to each arc and the entire network topology and arc weights are known to each router. Each router computes a graph of shortest weight paths from itself to every other router in the network. Traffic is routed on the shortest weight paths. All traffic leaving router s with destination ro...

A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment, topological routing, and geometric...

A unique method has been developed to scavenge energy from monocrystaline solar cells to power wireless router nodes used in indoor applications. The system’s energy harvesting module consists of solar cells connected in series-parallel combination to scavenge energy from 34W fluorescent lights. A set of ultracapacitors were used as the energy storage device. Two router nodes were used as a rou...

The function of a router is to switch arriving packets to their correct output destination. A router is built to achieve a specified capacity (the sum of the rates of its interfaces), and users expect a router to consistently achieve this capacity. However, no commercial high-speed router can guarantee today that it will achieve its full capacity for all arrival traffic patterns. This is due to...

Communication in parallel computers requires a low latency router. Once a suitable routing algorithm is selected, an implementation must be designed. Issues such as whether the router should be input or output driven need to be considered. In this paper, we use simulations to compare input driven and output driven routing algorithms. Three algorithms, the Dally-Seitz oblivious router, the *-cha...

An even-wiring router for the BGA package is presented in this paper to interconnect each I/O pad of a chip to a corresponding ball distributed on the substrate area. The major phases for the router consist of layer assignment, topological routing, and physical routing. Using this router, we can generate an even distribution of planar and any-angle wires to improve manufacturing yield. We have ...

In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 7× 7 crossbar to achieve the frequency of 1.25GHz in TSMC 65nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes l...

In the conceptual sending algorithm in [ND] and in the optional extension in [ROUTERSEL], a next hop is chosen when no destination cache entry exists for an off-link destination or when communication through an existing router is failing. Normally, a router is selected the first time traffic is sent to a specific destination IP address. Subsequent traffic to the same destination address continu...