A 16kb lTlC FeRAM testchip is designed and fabricated in a 0.35pm FeRAM process. The testchip uses a reference generation scheme that balances fatigue evenly between memory cells and reference cells, hence providing the lTlC cell with 2T2C robustness to fatigue. The testchip achieves an access time of 6211s at 3V. Introduction Reference generation is an essential component of lT lC Ferroelectri...
