© 2010 Sang-In Cho et al. 1 In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultrawideband systems. The proposed 128-point FFT processor employs both a modified radix-2 algorithm and a radix-2 algorithm to significantly reduce the numbers of complex constant multipliers and complex booth mul...

Many multimedia and DSP applications are highly multiplication intensive so that the performance and power consumption of these systems are dominated by multipliers. The computation of the multipliers manipulates two input data to generate many partial products for subsequent addition operations, which in the CMOS circuit design requires many switching activities. Thus, switching activity withi...

ion, 7Additionblock carry lookahead generator (BCLG), 36carry lookahead adder (CLA), 34carry lookahead generator (CLG), 34carry propagate addition (CPA), 29carry select adder (CSEA), 43carry skip adder (CKSA), 40generate, 29half adders, 28prefix adder, 49propagate, 29reduced full adder (RFA), 38ripple carry adder (RCA), 30ripple carry adde...

Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In our project we try to determine the best solution to this pro...

The FFT processor is a critical block in all multi-carrier systems used primarily in the mobile environment. The portability requirement of these systems is mainly responsible for the need of low power FFT architectures. In this study, an efficient addressing scheme for radix-4 64 point FFT processor is presented. It avoids the modulo-r addition in the address generation; hence, the critical pa...

In this paper, we present a 128-point FFT/IFFT processor for ultrawideband (UWB) systems. The proposed FFT is developed based on the higher radix -2 4 . It reduces computational complexity and hardware requirement compared to conventional radix -2 FFT. Since the proposed pipelined architecture for 128-point FFT is designed using mixed-radix (16+8) multipath delay feedback (MRMDF). The proposed ...

In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (N/r), but also eliminates the need of pre-computing odd multiples of the multiplicand in higher radix (r≥3) multiplication. Based on a mathematical proof t...

Modular arithmetic operations (inversion, multiplication and exponentiation) are used in several cryptography applications. RSA and elliptic curve cryptography (ECC) are two of the most well established and widely used public key cryptographic (PKC) algorithms. The encryption and decryption of these PKC algorithms are performed by repeated modulo multiplications. These multiplications differ fr...

A generic M-ary continuous phase modulation (CPM) scheme, with a modulation index of h = M 1 , can be decomposed into a continuous-phase encoder (CPE) followed by a memoryless modulator (MM), where the CPE is linear over the ring of integers modulo M (M being the code radix). Thus, for a binary CPM scheme, M = 2 while for a quaternary scheme, M = 4. By designing a channel encoder (CE), which is...