This paper presents ultra-low voltage transconductor using a new bulk-driven quasi-°oatinggate technique (BD-QFG). This technique leads to signi ̄cant increase in the transconductance and the bandwidth values of the MOS transistor (MOST) under ultra-low voltage condition. The proposed CMOS structure of the transconductor is capable to work with ultra-low supply voltage of 300mV and low power con...

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in...

We have demonstrated a room-temperature silicon single-electron transistor memory that consists of ~i! a narrow channel metal-oxide–semiconductor field-effect transistor with a width ~;10 nm! smaller than the Debye screening length of single electron; and ~ii! a nanoscale polysilicon dot ~;737 nm! as the floating gate embedded between the channel and the control gate. We have observed that stor...

In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are gi...

Detection of floating-point rounding errors normally requires run-time analysis in order to be effective and software-based tools are seldom used due to the extremely high computational demands. In this paper we present a field programmable gate array (FPGA) based floating-point coprocessor which supports standard IEEE-754 arithmetic, user selectable precision and Monte Carlo Arithmetic (MCA). ...

In this paper we present a 2 input analog Current-Starved Pseudo-Floating Gate (CSPFG) inverter with capacitive feedback. The analog CSPFG inverter suppresses low frequencies due to the active, local feedback. This inverter can be used in designing filters where a narrow band pass or reject is the main goal. Typical applications are detection of high frequency components in sensor signals, i.e....

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices base...

Low voltage (LV) analog circuit design techniques are addressed in this tutorial. In particular, (i) technology considerations; (ii) transistor model capable to provide performance and power tradeoffs; (iii) low voltage implementation techniques capable to reduce the power supply requirements, such as bulk-driven, floating-gate, and self-cascode MOSFETs; (iv) basic LV building blocks; (v) multi...

We have developed an amplifier which removes its "offset" as a natural part of its operation by modifying the charge on a floating gate. The charge on the floating gate is adapted by a combinat,ion of electron tunneling and hot-electron injection, resulting in a nonlinear high-pass filter with a cutoff frequency less than 1 Hz. We show experimental data from this autozeroing amplifier for vario...

As NAND Flash memory process technology scales below 32nm and the number of charge levels per cell exceeds four, cell threshold voltage distributions must be narrower in order to prevent errors resulting from distribution overlap [3, 5, 6]. An obstacle to achieving narrow distributions is the floating-gate (FG) to floating-gate coupling [4, 6]. This coupling shifts the threshold voltages by a d...