We present a novel test methodology for testing IP cores in SoCs with embedded processor cores. The methodology uses the processor core to run a test program to deliver test patterns to the target IP cores in the SoC and analyze the test responses. The test program can also use the processor core to generate test patterns. This provides tremendous flexibility in the type of patterns that can be...

1 Henrique Cota de Freitas, Pontifical Catholic University of Minas Gerais, Post -Graduation Program in Electrical Engineering Student, 500 Av. Dom Cabral Coração Eucarístico Belo Horizonte Minas Gerais, [email protected] 2 Carlos Augusto Paiva da Silva Martins, Pontifical Catholic University of Minas Gerais, Post -Graduation Program in Electrical Engineering Professor, 500 Av. Dom Cabral, Coraç...

Modern processors are very advanced but still suffer the bottleneck of slow memory access speeds. Processors now have the ability to run multiple tasks in parallel. This means that the processor runs multiple tasks concurrently, rather than sequentially, thus reducing the effect of memory access times. Utilizing this ability is called parallelization. There are many standards in place that allo...

With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten development period and reduce the power consumption. To this end, the compiler for a multi core processor is expected not only to parallelize program effectively, but also to control the voltage and clock frequency of processors...

This paper presents some compiler and program transformation techniques for concurrent multithreaded architectures, in particular the superthreaded architecture 9], which adopts a thread pipelining execution model that allows threads with data dependences and control dependences to be executed in parallel. In this paper, we identify several important program analysis and transformation techniqu...

This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test vectors for each core are compressed using matrix-based operations that significantly reduce the amount of test data that needs to be stored on the tester. The compressed data is transferred from the tester to the proce...

This paper illustrates a formal technique for describing the timing properties and resource constraints of pipelined superscalar processor instructions at high level. Superscalar processors can issue and execute multiple instructions simultaneously. The degree of parallelism depends on the multiplicity of hardware functional units as well as data dependencies among instructions. Thus, the timin...

The Mayfly, a parallel processor being built at HP Labs in Palo Alto, has architectural support for several important aspects of the OM virtual machine for parallel logic programs. Each node has an extra processor that is able to relieve the main processor of a significant amount of the “housekeeping” work of memory management, task switching, and message handling. This paper describes how the ...

We consider a generalization of the SPMD programming model to orthogonal processor groups. In this model different partitions of the processors into disjoint processor groups can be exploited in a single parallel implementation. The parallel programming model is appropriate for grid based applications with computations and dependence pattern mainly aligned in horizontal or vertical directions. ...

In this paper, we introduce the Datarol-II processor, that can e ciently execute a ne-grain multi-thread program, called Datarol. In order to achieve the e cient multi-thread execution by reducing context switching overhead, we introduce an implicit register load/store mechanism in the execution pipeline. A two-level hierarchical memory system is also introduced in order to reduce memory access...