A frequency divider based on injection-locked tunable ring oscillator is designed on 0.13-μm standard CMOS. The proposed design can achieve divide-by-4 in the frequency range of 58.75-66.3 GHz. The divider dissipates 49.5 to 54.5 mW power from a 1.5-V voltage supply. Key-Words: High-speed frequency dividers, Injection-locked tunable ring oscillator, Division range

An ultra-wide locking range transformer-based injection-locked frequency divider (ILFD) is presented. By making use of a 4-order transformer-based resonator and an inductive gain peaking technique, the proposed ILFD can achieve high performance in terms of wide locking range and low power consumption. Fabricated in a standard 65nm CMOS process with a core area of 0.18mm, the ILFD measures a loc...

A unequal Wilkinson power divider based on asymmetrical coupled line section is presented in this paper. The proposed unequal Wilkinson power divider topology uses asymmetrical coupled-line section and two transmission-line transformers. For simplification, a section asymmetrical coupled line is applied to obtain front compact matching structure. For generalization, three ports terminated imped...

a power divider (pd)/ power combiner (pc) with high quality factor and enhanced output ports isolation using substrate integrated waveguide (siw) technology is proposed. an siw cavity is designed to provide a high quality factor filtering response and an smd resistor is attached between two output ports to realize the high isolation. the value of the applied resistor is calculated by using the ...

In this paper, the design of equal-split quad-band Wilkinson power divider is presented. The design consists of two quad-band transmission line transformers and four isolation resistors. Standard transmission line theory and even/odd modes analyses are used to obtain closed form expressions that are solved using particle swarm optimization technique to find the required divider parameters (leng...

A high-speed triple-modulus frequency divider (FD) is designed and fabricated in a 90-nm CMOS process. With three pairs of nMOS switches inserted in the signal paths of the regenerative divider, the FD can offer three selectable division ratios of 1/2, 1/3, and 1/4. The corresponding behavior model of the proposed divider is utilized to explain the operation principle and analyze the locking ra...

This work describes the design of a divder technique Low-power techniques are applied in the design of the unit, and energy-delay tradeoffs considered. The energy dissipation in the divider can be reduced by up to 70% with respect to a standard implementation not optimized for energy, without penalizing the latency. In this dividing technique we compare the radix-8 divider is compared with one ...