In this paper, a novel implementation of 8x8 Multiplier using 4-2 Compressors is presented; which produces quick results, especially for use in Digital Signal Processors and in Microprocessors. This multiplier uses a new partial-product reduction format which consecutively reduces the maximum output delay. The new design of multiplier requires less number of MOSFET’s compared to Wallace Tree Mu...

Power optimization is the major problem in digital circuit design. In this paper using MTCMOS and stack techniques are proposed. Multi threshold CMOS sleep stack and logic stack, super cutoff sleep stack and logic stack are proposed. Stacking is introduced in MTCMOS concept which decreases leakage power based on the power dissipation of pMOS and nMO Stransistor. MTCMOS technique uses multiple v...

A binary comparator architecture is proposed in this work for static logic to achieve both low-power and high-performance operations. It also presents a detailed timing performance power analysis of various state-of-the-art designs. The main advantages design are its high speed efficiency maintained over wide range operands size, which useful at low-input data activity environments. circuit use...

A modified approach for Feed-Through logic (FTL) is developed in this paper to provide improved power delay product (PDP). FTL is examined against proposed approach, by analysis through computer simulation. It is shown that the modified FTL has low power consumption and high speed over existing FTL. Based on the performance the given approach is found very efficient for high speed arithmetic or...

The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power...

In this paper, a full adder cell based on majority function using Carbon-Nanotube Field-Effect Transistor (CNFET) technology is presented. CNFETs possess considerable features that lead to their wide usage in digital circuits design. For the design of the cell input capacitors and inverters are used. These kinds of design method cause a high degree of regularity and simplicity. The proposed des...

This paper presents low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed names as Braun multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier and these mu...

In this paper different low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 250MHz and 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed which are Array multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multipl...

Clustered voltage scaling scheme is an effective method of power consumption reduction without performance degradation. One of the main issues in this scheme is performance and power penalties due to insertion of level converting flip-flops at the interface from low-supply to high supply clusters to simultaneously perform latching and level converting functions. A new level converting flip-flop...