due to the high density and the low consumption power in the digital integrated circuits, mostly technology of cmos is used. during the past times, the metal oxide silicon field effect transistors (mosfet) had been used for the design and implementation of the digital integrated circuits because they are compact and also they have the less consumption power and delay to the other transistors. b...

A 90nm CMOS, 64Kbit, 1.16GHz, 16 port SRAM with multi-bank architecture realizing 590Gbps random access bandwidth, 41mW power dissipation at 1GHz and 0.91mm2 (13.9μm2/bit) area consumption is reported. Compared to conventional 16 port SRAM data, area and power consumption are reduced by factors 16 and 5, respectively, while maximum clock frequency is about a factor 2 higher.

A new approach for designing an ultra wideband (UWB) CMOS low noise amplifier (LNA) is presented. The aim of this design is to achieve a low noise figure, reasonable power gain and low power consumption in 3.1-10.6 GHz. Also, the figure of merit (FOM) is significantly improved at 180nm technology compared to the other state-of-the-art designs. Improved π-network and T-network are used to obt...

Due to the high density and the low consumption power in the digital integrated circuits, mostly technology of CMOS is used. During the past times, the Metal oxide silicon field effect transistors (MOSFET) had been used for the design and implementation of the digital integrated circuits because they are compact and also they have the less consumption power and delay to the other transistors. B...

SRAM occupies two-third area of VLSI chips, therefore it dominates the total power consumption. To enhance the performance of these chips, SRAM cell should meet the requirement of lesser power consumption. This paper presents a new 8T SRAM cell that is efficient in Dynamic power consumption in Write mode and Leakage power consumption when compared with referred 9T SRAM cell and standard 6T SRAM...

this paper presents a new method to reduce consumption power in flash adc in 65nm cmos technology. this method indicates a considerable reduction in consumption power, by removing comparators memories. the simulations used a frequency of 1 ghz, resulting in decreased consumption power by approximately 90% for different processing corners. in addition, in this paper the proposed method was desig...

An ultra-low power area-efficient fully differential multi-bit quantizer used in Sigma-Delta modulator (SDM) is presented. The quantizer is named as capacitor-string area-efficient (CSAE) quantizer since instead of the typical resistor string, it employs a capacitor string to avoid static power consumption. Furthermore, a novel circuit configuration with saving half number of comparators is app...

the existing studies of threshing process of combine harvesters adopt the assumption of constant mass, which is contradictory to the phenomenon of separation of grains and short stalks in actual threshing process. therefore, the characteristics of threshing and separation are not accurately described. aiming at this problem, this study established the tangential-longitudinal threshing and separ...

In this paper low power consumption amplifier is presented. Low power consumption amplifier is versatile demanded in modern technology, modern technology want such type of amplifier which gives low power consumption with less reflection, in this paper presented series and shunt feedback topology with pole zero compensation method for designing of low power consumption amplifier, Today the deman...