Index Terms Computer Science [1] Fahim, A. M. And Elmasry, M. I. 2003. A Fast Lock Digital Phase-locked-loop Architecture For Wireless Applications, Ieee Transactions On Circuits And Systems-ii: Analog And Digital Signal Processing, Vol. 50, No. 2, Feb. , 2003. [2] Saber, M. , Jitsumatsu,y. And Khan, M. t. a. 2010. Design And Implementation Of Low Power Digital Phase-locked Loop, Proceedings Of...

Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, phase locked loop fractional architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is b...

A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequency-locked loop and a fine phase-locked loop with smooth switching to prevent adverse interaction and false locking. Fabricated in a 0.18-μm CMOS process, the recovered clock exhibits a peak-topeak jitter of 60ps for a 2-Gb/s PRBS-7 data and a phase noise of –93.5 dBc/Hz at 1-MHz offset. The cor...

1 The PLL (Phase Lock Loop) can synchronize with a deterministic input wave or with a random input symbols. In the first case we have a WPLL (Wave Phase Lock Loop) and in the second case we have a SPLL (Symbol Phase Lock Loop. The WPLL (Wave Phase Lock Loop) is also known as WLL (Wave Lock Loop) or only PLL (Phase Lock Loop). The SPLL (Symbol Phase Lock Loop) is also known as SLL (Symbol Lock L...