the impulse response can be either finite or infinite. The methods for designing and implementing these two filter classes differ considerably. Finite impulse response (FIR) filters are digital filters whose response to unit impulse (unit sample function) is finite in duration. This paper presents the design of low power FIR filter and area efficient parallel linear phase FIR digital filter. Lo...

This Paper presents an efficient implementation of high speed multiplier using the shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In This paper we compare the working of the three multipliers by implementing each of them separately in FIR filter. The parallel multipliers like radix2 and radix4 modified booth multiplier does the computations using lesser adders and l...

In this paper, we present flexible multi-precision multiplier that combined variable precision, parallel processing (PP), razor based dynamic voltage scaling (DVS), and dedicated MP operand scheduling to provide optimum performance for variety of operating conditions. All of the building blocks of proposed flexible multiplier can either work as independent small precision multiplier or parallel...

A low-power parallel multiplier based on optimized bypassing architecture (OBA) is proposed. The proposed OBA has two kinds of adder cells to reduce power consumption by 15.7 %. One is the two-dimensional bypassing adder (TDBA) which performs both row and column bypassing scheme simultaneously, and the other is the modified row-bypassing adder (MRBA) for the proposed row-bypassing scheme. In th...

In this paper a new low complexity parallel multiplier for characteristic two finite fields GF (2) is proposed. In particular our multiplier works with field elements represented through both Canonical Basis and Type I Optimal Normal Basis (ONB), provided that the irreducible polynomial generating the field is an All One Polynomial (AOP). The main advantage of the scheme is the resulting space ...

JCHPS Special Issue 8: December 2016 www.jchps.com Page 9 Design of Low-Power Specific Parallel Array Multipliers C Vivek*, R. Subalakshmi Department of Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Tamil Nadu. *Corresponding author: E-Mail: [email protected] ABSTRACT Multipliers play a critical part in recent digitalized life. In this advanced spher...

AbstractIn this work faster column compression multiplication has been achieved by using a combination of two design techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the final addition using a hybrid adder proposed in this work. Based on the proposed techniques 8, 16, 32 and 64bit Dadda multipliers are developed and com...

In this paper, a generalized Montgomery multiplication algorithm in GF(2m) using the Toeplitz matrix-vector representation is presented. The hardware architectures derived from this algorithm provide low-complexity bit-parallel systolic multipliers with trinomials and pentanomials. The results reveal that our proposed multipliers reduce the space complexity of approximately 15% compared with an...

An internally analog, externally digital architecture for parallel vector–matrix multiplication is presented. A threetransistor unit cell combines a single-bit dynamic random-access memory and a charge injection device binary multiplier and analog accumulator. Digital multiplication of variable resolution is obtained with bit-serial inputs and bit-parallel storage of matrix elements, by combini...

New bit-parallel dual basis multipliers using the modified Booth s algorithm are presented. Due to the advantage of the modified Booth s algorithm, two bits are processed in parallel for reduction of both space and time complexities. A multiplexer-based structure has been proposed for realization of the proposed multiplication algorithm. We have shown that our multiplier saves about 9% space co...