Reversible sequential circuits are going to be the significant memory blocks for the forthcoming computing devices for their ultra low power consumption. Therefore design of various types of latches has been considered a major objective for the researchers quite a long time. In this paper we proposed efficient design of reversible sequential circuits that are optimized in terms of quantum cost,...

Reversible logic has attracted much research interest over the last few decades, especially due to its application in quantum computing. In the construction of reversible gates from basic gates, ancilla bits are commonly used to remove restrictions on the type of gates that a certain set of basic gates generates. With unlimited ancilla bits, many gates (such as Toffoli and Fredkin) become unive...

Under ideal conditions, Reversible logic gates produce zero power dissipation. So these can be used for low power VLSI design. This paper proposes a new reversible parallel adder/subtractor using 4*4 Reversible DKG gate that can work singly as a reversible full adder and a full subtractor. A serial adder/subtractor is also designed in this paper using Reversible Universal Shift registers and DK...

This project revolves around the design and implementation of floating point adder architecture using reversible logic to improve the design in terms of the number of garbage outputs and the number of gates used. In recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology and optical computing because of it...

Reversible computing has been studied since Rolf Landauer advanced the argument that has come to be known as Landauer's principle. This principle states that there is no minimum energy dissipation for logic operations in reversible computing, because it is not accompanied by reductions in information entropy. However, until now, no practical reversible logic gates have been demonstrated. One of...

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Firstly, this paper proposes novel two transistor AND & OR gates. The proposed AND gate has no power supply, thus it can be referred as the Powerless AND gate. Similarly, the proposed two transistor OR gate has no ground and can be referred as Grou...

In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable at the circuit’s outputs. Thus reversible logic circuits that are parity preserving will be beneficial to the development of fault tolerant systems in nanotechnology. This paper presents an efficient realization of well ...

Reversible quantum computer is gaining interest for the future computer system. With the advent of quantum computer and reversible logic, design and implementation of all devices has received more attention. BCD digit adder is the basic unit of the more precise decimal computer arithmetic. The research objective is to increase speed of operation for addition of BCD numbers while minimizing the ...

We present a collection of results concerning the structure of reversible gate classes over non-binary alphabets, including (1) a reversible gate class over non-binary alphabets that is not finitely generated (2) an explicit set of generators for the class of all gates, the class of all conservative gates, and a class of generalizations of the two (3) an embedding of the poset of reversible gat...

В работе рассматривается вопрос сложности обратимых схем, состоящих из функциональных элементов NOT, CNOT и 2-CNOT и имеющих малое число дополнительных входов. Изучается функцииШеннонa сложности L(n, q) обратимой схемы, реализующей отображение f : Zn2 → Z n 2 , при условии, что количество дополнительных входов q 6 O(n). Доказывается оценка L(n, q) ≍ n2n / log 2 n для указанного диапазона значен...