. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Table of

Networks on Chip (NoCs) have been steadily investigated from reliability, efficiency, and performance perspectives.However, little effort has been directed towards the security of complex on-chip networks. These networks are prone to attacks similar to those perpetrated against large scale networks such as datacenters and the internet. If a single core within an NoC is compromised, it can be us...

Nowadays Network-on-Chips is used instead of System-on-Chips for better performance. This paper presents a new algorithm to find a shorter path, and shows that genetic algorithm is a potential technique for solving routing problem for mesh topology in on-chip-network.

While multi-processor system-on-chips (MPSOCs) with network-on-chip (NOC) interconnect are becoming increasingly common to meet the constant performance demand, it is due to communication delays in the NOC extremely complicated to ensure that software executes correctly. In this paper, we extend our architecture that non-intrusively observes global properties at run time using distributed monit...

Network-on-Chip (NoC) as a promising design approach for on-chip interconnect fabrics could overcome the energy as well as synchronization challenges of the conventional interconnects in the gigascale System-on-Chips (SoC). The advantages of communication performance of traditional wired NoC will no longer be continued by the future technology scaling. Packets that travel between distant nodes ...

The goal of this end of term work is to evaluate the impact of the Network-on-Chip (NoC) parameters over the performance of applications on Multiprocessors Systems-on-Chip (MPSoCs). Nowadays, MPSoCs have so many constraints of performance that bus-based communications are not able to achieve the full potential of MPSoCs. Therefore, the adoption of networks-on-chip (NoCs) is a trend for the comm...

Journal of Electronic Systems Volume 6 Number 2 June 2016 ABSTRACT: The power dissolute by the links of a network-on-chip (NoC) starts to play with the power dissipated by the additional basic elements of to the communication sub-system within specifically, the routers &network interfaces (NIs). In this, we present a conventionaldata encoding schemes meant to reducing the dissipated of power by...

With the progress of deep submicron technology power consumption and temperature related issues have become two of the most critical aspects for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an ever increasing thermal stress. This necessitates effective mechanisms for thermal management. In this paper we propose to precompute and proactiv...

The Network on Chip (NoC) paradigm is rapidly replacing bus based System on Chip (SoC) designs due to their inherent disadvantages such as non-scalability, saturation and congestion. Currently very few tools are available for the simulation and evaluation of on-chip architectures. This study proposes a generic object oriented model for performance evaluation of on-chip interconnect architecture...