While a communication network is a critical component for an efficient system-on-chip multiprocessor, there are few approaches available to help with system-level architectural exploration of such a specialised interconnection network. This paper presents an integrated modelling, simulation and implementation tool. The network architecture can be co-simulated with embedded-software to obtain cy...

In the purely object-parallel approach to multiprocessor rendering, each processor is assigned responsibility to render a subset of the graphics database. When rendering is complete, pixels from the processors must be merged and globally z-bu ered. On an arbitrary multiprocessor interconnection network, the straightforward algorithm for pixel merging requires dA total network bandwidth per fram...

Novel, cheap optical components allow for reconfigurable interconnection networks inside multiprocessor systems. In this paper, we introduce some of these components, their limitations, and present simulations that show the resulting speedup of these multiprocessor systems.

Machine learning techniques are applicable to computer system optimization. We show that shared memory multiprocessors can successfully utilize machine learning algorithms for memory access pattern prediction. In particular three different on-line machine learning prediction techniques were tested to learn and predict repetitive memory access patterns for three typical parallel processing appli...

RECONFIGURATION IN AN OPTICAL MULTIRING INTERCONNECTION NETWORK by Praveen Krishnamurthy ADVISOR: Professor Roger D. Chamberlain December, 2002 Saint Louis, Missouri The advent of optical technology that can feasibly support extremely high bandwidth chip-to-chip communication raises a host of architectural questions in the design of digital systems. Terabit per second (and higher) bandwidths ha...

The optimization of the irregular connection network of the multiprocessor systems with the distributed memory is the NP complete problem which is generally compute-intensive process. Graphics processing units provide a large computational power at a very low price allowing the fine-grained parallelism. This work investigates the use of the GPU in the parallelisation of the optimal irregular ne...

In this paper, we present a systematic design and implementation of reconfigurable interconnects on demand. The proposed on-chip interconnection network provides identical physical topologies to logical topologies for given applications. The network has been implemented with parameterized switches, dynamically multiplexed by a traffic controller. Considering practical media applications, a mult...

In a parallel processing system, Multi-stage Interconnection Networks (MINs) play a vital role in making the network reliable and cost effective. The MIN is an important piece of architecture for a multiprocessor system, and it has a good impact in the field of communication. Optical Multi-stage Interconnection Networks (OMINs) are the advanced version of MINs. The main problem with OMINs is cr...

with the task placement problem in a straight way that allows us to go one step further, we have adopted an interconnection-network-based DRHW mode, which includes Operating System support to reallocate tasks at run-time. On top of this model we have applied an emerging task concurrency management (TCM) methodology initially developed for multiprocessor platforms with promising results. Moreove...

Self-tuning, a technique devised by Ted Kehl, is a new clocking paradigm which incorporates the best features of conventional synchronous logic along with advantages offered by the asynchronous, self-timed paradigm. The principles of self-tuning are explained and an outline of the application of self-tuning to the interconnection network of a large scale distributed shared memory multiprocessor...