Multi-value logic is defined as a non-binary logic and involves the switching between more than two states. The design of Multiple Valued Logic (MVL) digital circuits is performed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. More data can be transmitted by single wire having more than two levels. Multiple-valued logic (MVL) application in t...

The paper proposes mvTANTs , three-level networks with multiple-valued inputs and binary outputs. These networks are a generalization of binary T A N T s (Three level And Not networks with True Inputs). One of possible interpretations of m v T A N T is a four-level binary network with input decoders which realize multiplevalued literals. Similarly to mvPLAs, mvTANTs have regular structures with...

Positive definite operator-valued kernels generalize the well-known notion of reproducing kernels, and are naturally adapted to multi-output learning situations. This paper addresses the problem of learning a finite linear combination of infinite-dimensional operator-valued kernels which are suitable for extending functional data analysis methods to nonlinear contexts. We study this problem in ...

In a civilization, human labor of one type is exchanged for human labor of another type. For example, when one eats at a restaurant, one exchanges money earned from one’s own labor for the labor of people who cook, raise animals and vegetables, deliver goods, etc.. This exchange is made possible by a salary, which establishes a value for labor of different types. There are many ways to represen...

This paper presents a system for the automatic generation of Galois-field (GF) arithmetic circuits, named the GF Arithmetic Module Generator (GF-AMG). The proposed system employs a graph-based circuit description called the GF Arithmetic Circuit Graph (GF-ACG). First, we present an extension of the GF-ACG to handle GF(pm) (p ≥ 3) arithmetic circuits, which can be efficiently implemented by mult...

In VLSI, crossings occupy space and cause delay. Therefore, there is significant benefit to planar circuits. We propose the use of planar multiple-valued decision diagrams to produce planar multiple-valued circuits. Specifically, we show conditions on 1) threshold functions, 2 symmetric functions, and 3) monodiagrams. Our results apply to binary functions, as well. For example, we show that all...

We introduce the reduced signed logics which generalize previous approaches to signed logics in the sense that each variable is allowed to have its own set of semantic values. Reductions on both signed logics and signed formulas are used to describe improvements in tableau provers for MVLs. A labelled deductive system allows to use the implicit information in the formulas to describe improved e...