A multiple-output function can be represented by a binary decision diagram for characteristic function (BDD for CF). This paper presents a method to represent multiple-output incompletely specified functions using BDD for CFs. An algorithm to reduce the widths of BDD for CFs is presented. This method is useful for decomposition of incompletely specified multiple-output functions. Experimental r...

The use of Look-Up Tables (LUTs) is extended from binary to multiple-valued logic (MVL) circuits. A multiple-valued LUT can be implemented using both current-mode and voltage-mode techniques, reducing the transistor count to half compared to that of a binary implementation. Two main applications for multiple-valued LUTs are multiple-valued FPGAs and intelligent memories. An FPGA uses a LUT as a...

This paper presents a hybrid logic simulator using both an event-driven and a cycle-based methods. For special primitives such as memories and tri-state buffers, it uses an event-driven method. For other parts, it uses a cyclebased method using LUT cascade emulators. To simulate a large scale circuit, it partitions the circuit into smaller ones, and realizes each part by an LUT cascade emulator...

This paper presents a method for operational testing of a memristor-based look-up table (LUT) memory block. In the proposed method the deterioration of the memristors (as storage elements of a LUT), is modeled based on the reduction of the resistance range, a phenomenon well known as reported in the technical literature. A quiescent current technique is used to diagnose the memristors when dete...

The Peak Dynamic Power Estimation (PDPE) problem involves finding input vector pairs that cause maximum power dissipation (maximum toggles) in circuits. The PDPE problem is essential for analyzing the reliability and performance of digital circuits prior to fabrication. This paper proposes a methodology for solving the PDPE problem on circuits mapped onto Field Programmable Gate Arrays (FPGAs)....

To generate ideal digital holograms, a computer-generated hologram (CGH) has been regarded as a solution. However, it has an unavoidable problem in that the computational burden for generating CGH is very large. Recently, many studies have been conducted to investigate different solutions in order to reduce the computational complexity of CGH by using particular methods such as look-up tables (...

Control of the lower urinary tract (LUT) requires complex neuronal circuits that involve elements located at the peripheral nervous system and at different levels of the central nervous system. Spinal cord injury (SCI) interrupts these neuronal circuits and jeopardizes the voluntary control of bladder function. In most cases, SCI results in a period of bladder areflexia, followed by the emergen...

Detecting delay faults in SRAM-FPGAs can be done resorting to BIST. In this context, the objective of this paper is to analyse the timing behaviour of Look-Up Tables (LUT) contained in FPGAs in both fault-free and delay faulty cases. We first show that the propagation delay of a LUT depends both on the transition pattern applied to its inputs and on the function implemented in it. This signific...

Diffuse optical spectroscopy (DOS) provides a powerful tool for fast and noninvasive disease diagnosis. The ability to leverage DOS to accurately quantify tissue optical parameters hinges on the model used to estimate light-tissue interaction. We describe the accuracy of a lookup table (LUT)-based inverse model for measuring optical properties under different conditions relevant to biological t...

This paper presents the realization of memory efficient architecture using Distributed Arithmetic (DA) for implementation of Finite Impulse Response (FIR) filter. Here, the multipliers in FIR filter are replaced with multiplier less DA based technique. First, the theory of DA is described. In this technique, pre-computed values of inner product are stored in LUT, which are further added and shi...