The paper offers a new methodology of designing in CMOS technology analogdigital artificial neurons learnable to arbitrary logical threshold functions of some number of variables. The problems of functional ability, implementability restrictions, noise stability, and refreshment of the learned state are formulated and solved. Some functional problems in experiments on teaching an artificial neu...

This paper offers a new methodology for designing in CMOS technology analog-digital artificial neurons training on arbitrary logical threshold functions of some number of variables. The problems of functional ability, implementability restrictions, noise stability, and refreshment of the learned state are formulated and solved. Some functional problems in experiments on teaching logical functio...

Abstract The living mycelium networks are capable of efficient sensorial fusion over very large areas and distributed decision making. information processing in the is implemented via propagation electrical chemical signals en pair with morphological changes structure. These mechanisms manifested experimental laboratory findings that show exhibit rich dynamics neuron-like spiking behaviour a wi...

We consider the problem of mapping a logical quantum circuit onto given hardware with limited 2-qubit connectivity. model this as an integer linear program, using network flow formulation binary variables that includes initial allocation qubits and their routing. several cost functions: approximation fidelity circuit, its total depth, measure cross-talk, all which can be incorporated in model. ...

Synthetic gene circuits often require extensive mutual optimization of their components for successful operation, while modular and programmable design platforms are rare. A possible solution lies in the 'bow-tie' architecture, which stipulates a focal component-a 'knot'-uncoupling circuits' inputs and outputs, simplifying component swapping, and introducing additional layer of control. Here we...

We model sequential synchronous circuits on the logical level by signal-processing programs in an extended lambda calculus Lpor with letrec, constructors, case and parallel or (por) employing contextual equivalence. The model describes gates as (parallel) boolean operators, memory using a delay, which in turn is modeled as a shift of the list of signals, and permits also constructive cycles due...

QDI Dual-rail asynchronous circuits, if implemented carefully balanced, have natural and efficient resistance to side-channel attacks in cryptography applications. Due to hardware redundancy in previous balanced gate designs, there are many faults which can make them imbalanced without causing logical errors. Therefore, traditional logical testing methods are unable to test and verify if a gate...

We study Life-like cellular automaton rule B2/S2345. This automaton exhibits a chaotic behavior yet capable for purposeful computation. The automaton implements Boolean gates via patterns which compete for the space when propagate in channels. Values of Boolean variables are encoded into two types of patterns — symmetric (False) and asymmetric (True). We construct basic logical gates and elemen...

Self-assembly of DNA is considered a fundamental operation in realization of molecular logic circuits. We propose a new approach to implementation of data flow logical operations based on manipulating DNA strands. In our method the logic gates, input, and output signals are represented by DNA molecules. Each logical operation is carried out as soon as the operands are ready. This technique empl...

The logic behavior and performance of ECL gates under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalent gates. Performance degradation faults such as delay, current and Volta...