نتایج جستجو برای: locked loop
تعداد نتایج: 142892 فیلتر نتایج به سال:
An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm and consumes 88 μW at 0.4-V supply for...
The standards governing the grid connection of distributed power generation systems (DPGS) are becoming increasingly demanding due to the growing number of alternative energies being connected to the grid. Grid connection standards now place greater emphasis on the fault ride-through capabilities of the DPGS. In order to fulfill these standards, improvements must be made to the grid-side contro...
1 The PLL (Phase Lock Loop) can synchronize with a deterministic input wave or with a random input symbols. In the first case we have a WPLL (Wave Phase Lock Loop) and in the second case we have a SPLL (Symbol Phase Lock Loop. The WPLL (Wave Phase Lock Loop) is also known as WLL (Wave Lock Loop) or only PLL (Phase Lock Loop). The SPLL (Symbol Phase Lock Loop) is also known as SLL (Symbol Lock L...
We point out that the μ-problem in theories in which supersymmetry breaking is communicated to the observable sector by gauge interactions is more severe than the one encountered in the conventional gravity-mediated scenarios. The difficulty is that once μ is generated by a one-loop diagram, then usually Bμ is also generated at the same loop order. This leads to the problematic relation Bμ ∼ μΛ...
In previous work, we have shown that second-order phase locked loop (PLL) with sinusoidal phase detector characteristics have a separatrix cycle for a certain value of closed loop gain. It was verified that bifurcation from a stable separatrix cycle is the mechanism responsible for breaking the limit cycle associated with the PLL’s out-of lock state and the loop pulls in (phase lock). The value...
Almost all logic systems have a main clock signal in order to provide a common timing reference for all of the components in the system. Supporting the highest bandwidth data rates among devices requires advanced clock management technology such as delay-locked loops (DLLs). The DLL circuitry allows for very precise synchronization of external and internal clocks. In this paper a low jitter and...
The aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. For this purpose, first, an exact mathematical model of phase locked loop (PLL) based frequency synthesizer is described and analyzed. Then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. Based on this formula, the phase ...
In this paper a new phase-frequency detector is proposed using transmission gates which can detect phase difference less than 500ps. In other word, the proposed Phase-frequency Detector (PFD) can work in frequencies higher than 1.7 GHz, whereas a conventional PFD operates at frequencies less than 1.1 GHz. This new architecture is designed in TSMC 0.13um CMOS Technology. Also, the proposed PFD a...
A digital implementation of a new technique that delivers an extremely accurate and stable phase locked loop system (PLL) is presented. The new technique uses competing phase and frequency loops to incorporate an accurate local reference frequency into the phase locked loop structure. Disturbances on the phase loop caused by the digital frequency loop are identified and a method to mitigate the...
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