In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, we present two methods to analyze the jitter tolerance of such links, based on statistical simulation of incoming data jitter and its effects on the recovered data bit error rate using Matlab. The second method is based on time-domain simulation using VHDL and...

The USB-IF designed the Receiver Jitter Tolerance Test to test the quality of the USB 3.0 receiver of a system. This test uses a waveform generator/oscilloscope combination, or a data generator/analyzer to send data to the Super Speed receiver which is then looped back through the transmitter back to the instrument. The data received is compared to the data generated and the errors are counted....

Jitter is extremely important in PLL based systems. The effects of jitter range from not having any effect on system operation to rendering the system completely non-functional. Reducing Jitter and power supply is one way to help to improve the system performance. This review will concentrate on jitter and power supply in PLL building blocks. KeywordsLOW POWER, LOW JITTER, PFD, PLL ____________...

In real-time control system, output jitter of a task is important when feedback control loops are implemented as execution of periodic tasks. Output jitter refers to the variation of response time of a periodic task. For the stability of the control system, output jitter should be reduced. This paper aims to reduce the output jitter of real-time tasks under EDF scheduling. The proposed scheme d...

In order to transfer voice or some other application requiring real-time delivery over a packet network, we need a de-jitter buffer to eliminate delay jitters. An important design parameter is the depth of the de-jitter buffer since it influences two important parameters controlling voice quality, namely voice-path delay and packet loss probability. In this paper, we propose and study several s...

As the communication speed/data rate approaches 1 Gb/s and beyond, timing jitter and amplitude noise become the major limiting factors for system performance. Traditional methods used in simulating, analyzing, modeling, and quantifying jitter and noise in terms of peak-to-peak and/or rms becomes no longer accurate and sufficient. As such, new methods with better accuracy and comprehension are c...

Timing signal jitter can have a profound impact on a wide variety of applications from analog radio frequency (RF) or audio-to-digital communications. While information in a communications system, for example, is extracted from serial data streams by sampling the data signal at specific points, the presence of small quantities of jitter can alter the edge positions enough to lead to data errors...