Layout design and the flow of materials have a significant impact on performance of manufacturing system (garments industry) .These can help to increase productivity, reduce work in process and inventory, short production lead time, streamlines the flow of materials, cost and reduce non value added activities from the production process of waiting and transportation, which make the factory meet...

This paper presents an adapted particle swarm optimization model for the electrical layout planning of floating offshore wind farms (FOWFs). A comprehensive is considered by taking into account entire turbine connection possibilities as well stochastic speed and direction computation wake effect within farm. Furthermore, dynamic power cables used turbines are their respective acquisition instal...

We present a recursive method for generating layout for VLSI chips which combines the flexibility of gate array and standard cell layout with the control and density of custom layout. The method allows seamless integration of hand-drawn and synthesized layout, so that hand layout need only be used where the increase in density is justified. Layout is generated automatically with predictable res...

The paper studies a unit cell mismatch scrambling method for high-resolution unary DAC based on virtual 3-dimensional (3D) layout, to improve its spurious-free dynamic range (SFDR) communication applications. This can be implemented with relatively simple interconnections and circuits, compared that the 2-dimentional (2D) layout.

The network architecture is based on the following principles: The network topology is a planar grid of switches that route the traffic according to fixed shortest path (X-Y based) discipline, thus minimizing hardware tables and traffic overheads. Buffer requirements are reduced by employing multi-class wormhole forwarding while allowing inter-class priorities. The layout of the

The size and parameter optimization for the 5-nm carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) cell was presented in Part I of this article. Based on that work, we propose a (CNT) SRAM array composed schematically optimized CNFET CNT interconnects. We consider interconnects inside metallic single-wall (M-SWCNT) bundles to represent metal layers 0 1 (M0 M1). ...

A characterization methodology to model interconnect capacitance for accurate circuit simulation is presented. The method utilizes a simple measurement scheme to measure inter-layer capacitances. The measured data is then used to tune a layout tool for accurate interconnect parasitic extraction. Results show good fit between simulated and measured ring oscillator speeds for a production 0.5μm, ...

In this paper, a robust optimization approach is proposed to design a dynamic cellular manufacturing system (DCMS) under uncertainty of processing time of products. In addition, a mathematical model considering cell formation, inter-cell design and production planning under a dynamic environment (i.e., product mix and demand are changed in each period) is presented. Therefore, reconfiguration b...