Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such processors will consume a significant fraction of the on-chip energy due to very wide fetch on each cycle. This paper proposes a new energy-effective design of the fetch unit that exploits the fact that not all instru...

Small filter caches (L0 caches) can be used to obtain significantly reduced energy consumption for embedded systems, but this benefit comes at the cost of increased execution time due to frequent L0 cache misses. The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by packi...

In this paper we present a novel processor hardware architecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dependences, the relatively small window size and the instruction fetch bandwidth. The new architecture executes simultaneously multiple threads of control obtained from a single program by means of control speculatio...

Energy consumption and power dissipation are important concerns in the design of embedded systems and they will become even more crucial with finer process geometry, higher frequencies, deeper pipelines and wider issue designs. In particular, the instruction cache consumes more energy than any other processor module, especially with commonly used highly associative CAM-based implementations. Tw...

This paper focuses on the instruction fetch resources in a real-time SMT processor to provide an energy-efficient configuration for a soft real-time application running as a high priority thread as fast as possible while still offering decent progress in low priority or non-realtime thread(s). We propose a fetch mechanism, Fetch-around, where a high priority thread accesses the L1 ICache, and l...

Abstract Architecture specifications such as Armv8-A and RISC-V are the ultimate foundation for software verification correctness criteria hardware verification. They should define allowed sequential relaxed-memory concurrency behaviour of programs, but hitherto there has been no integration full-scale instruction-set architecture (ISA) semantics with axiomatic models, either in mathematics or ...

There has been relatively little analytical work on processor optimizations for multimedia applications. With the introduction of MMX by Intel, it is clear that this is an area of increasing importance. Building on previous work [4, 5, 6, 7, 13, 14], we propose optimizations for multimedia architectures that support independent parallel execution of instructions within dynamically assembled tra...

In the present world the computer has become an essential and inevitable part in any field and industry be it in administrative field, science, defense or in any other field. The Processor designed and implemented is typical RISC machines following a 4-stage pipelining having instruction fetch (I-fetch), instruction decode, executing and storing (data memory operations and write back stages) fo...

Even sophisticated branch-prediction techniques necessarily suffer some mispredictions, and even relatively small mispredict rates hurt performance substantially in current-generation processors. This suggests the study of multipath execution, in which the processor simultaneously executes code from both the taken and not-taken outcomes of a branch. This paper describes HydraScalar, a simulator...

In the present world the computer has become an essential and inevitable part in any field and industry be it in administrative field, science, defense or in any other field. The Processor designed and implemented is typical RISC machines following a 4-stage pipelining having instruction fetch (I-fetch), instruction decode, executing and storing (data memory operations and write back stages) fo...